TMS320VC5502 datasheet(25/189 Pages) TI

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TMS320VC5502

Fixed-Point Digital Signal Processor

SPRS166H – APRIL 2001 – REVISED NOVEMBER 2004

Table 2-4. Signal Descriptions (continued)

MULTIPLEXED

OTHER(2)

FUNCTION

NAME

SIGNAL NAME

TYPE(1)

The C7 pin of the Parallel Port serves one of two functions: parallel general-purpose

input/output (PGPIO) signal PGPIO27 or external memory interface control signal

EMIF.CE3. The function of the C7 pin is determined by the state of the GPIO6 pin

I/O/Z

during reset. The C7 pin is set to PGPIO27 if GPIO6 is low during reset. The C7 pin

is set to EMIF.CE3 if GPIO6 is high during reset. The function of the C7 pin will be

set once the device is taken out of reset (RESET pin transitions from a low to high

C, D, E, F,

state).

G, H, M

Parallel general-purpose I/O. PGPIO27 is selected when GPIO6 is low during

PGPIO27

I/O/Z

reset. The PGPIO27 signal is configured as an input after reset.

EMIF chip-select for memory space CE3. EMIF.CE3 is selected when GPIO6 is

EMIF.CE3

O/Z

high during reset. The EMIF.CE3 signal is in a high-impedance state during reset

and is set to output after reset with an output value of 1.

The C8 pin of the Parallel Port serves one of two functions: parallel general-purpose

input/output (PGPIO) signal PGPIO28 or external memory interface control signal

EMIF.BE0. The function of the C8 pin is determined by the state of the GPIO6 pin

I/O/Z

during reset. The C8 pin is set to PGPIO28 if GPIO6 is low during reset. The C8 pin

is set to EMIF.BE0 if GPIO6 is high during reset. The function of the C8 pin will be

set once the device is taken out of reset (RESET pin transitions from a low to high

C, D, E, F,

state).

G, H, M

Parallel general-purpose I/O. PGPIO28 is selected when GPIO6 is low during

PGPIO28

I/O/Z

reset. The PGPIO28 signal is configured as an input after reset.

EMIF byte-enable 0 control. EMIF.BE0 is selected when GPIO6 is high during

EMIF.BE0

O/Z

reset. The EMIF.BE0 signal is in a high-impedance state during reset and is set to

output after reset with an output value of 1.

The C9 pin of the Parallel Port serves one of two functions: parallel general-purpose

input/output (PGPIO) signal PGPIO29 or external memory interface control signal

EMIF.BE1. The function of the C9 pin is determined by the state of the GPIO6 pin

I/O/Z

during reset. The C9 pin is set to PGPIO29 if GPIO6 is low during reset. The C9 pin

is set to EMIF.BE1 if GPIO6 is high during reset. The function of the C9 pin will be

set once the device is taken out of reset (RESET pin transitions from a low to high

C, D, E, F,

state).

G, H, M

Parallel general-purpose I/O. PGPIO29 is selected when GPIO6 is low during

PGPIO29

I/O/Z

reset. The PGPIO29 signal is configured as an input after reset.

EMIF byte-enable 1 control. EMIF.BE1 is selected when GPIO6 is high during

EMIF.BE1

O/Z

reset. The EMIF.BE1 signal is in a high-impedance state during reset and is set to

output after reset with an output value of 1.

The C10 pin of the Parallel Port serves one of two functions: parallel gen-

eral-purpose input/output (PGPIO) signal PGPIO30 or external memory interface

control signal EMIF.BE2. The function of the C10 pin is determined by the state of

C10

I/O/Z

the GPIO6 pin during reset. The C10 pin is set to PGPIO30 if GPIO6 is low during

reset. The C10 pin is set to EMIF.BE2 if GPIO6 is high during reset. The function of

the C10 pin will be set once the device is taken out of reset (RESET pin transitions

C, D, E, F,

from a low to high state).

G, H, M

Parallel general-purpose I/O. PGPIO30 is selected when GPIO6 is low during

PGPIO30

I/O/Z

reset. The PGPIO30 signal is configured as an input after reset.

EMIF byte-enable 2 control. EMIF.BE2 is selected when GPIO6 is high during

EMIF.BE2

O/Z

reset. The EMIF.BE2 signal is in a high-impedance state during reset and is set to

output after reset with an output value of 1.

The C11 pin of the Parallel Port serves one of two functions: parallel gen-

eral-purpose input/output (PGPIO) signal PGPIO31 or external memory interface

control signal EMIF.BE3. The function of the C11 pin is determined by the state of

C11

I/O/Z

the GPIO6 pin during reset. The C11 pin is set to PGPIO31 if GPIO6 is low during

reset. The C11 pin is set to EMIF.BE3 if GPIO6 is high during reset. The function of

the C11 pin will be set once the device is taken out of reset (RESET pin transitions

C, D, E, F,

from a low to high state).

G, H, M

Parallel general-purpose I/O. PGPIO31 is selected when GPIO6 is low during

PGPIO31

I/O/Z

reset. The PGPIO31 signal is configured as an input after reset.

EMIF byte-enable 3 control. EMIF.BE3 is selected when GPIO6 is high during

EMIF.BE3

O/Z

reset. The EMIF.BE3 signal is in a high-impedance state during reset and is set to

output after reset with an output value of 1.

Introduction

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