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TMS320VC5502 Datasheet(PDF) 179 Page - Texas Instruments |
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TMS320VC5502 Datasheet(HTML) 179 Page - Texas Instruments |
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179 / 189 page  www.ti.com 5.17 Inter-Integrated Circuit (I 2C) Timings IC10 IC8 IC4 IC3 IC7 IC12 IC5 IC6 IC14 IC2 IC3 IC13 Stop Start Repeated Start Stop SDA SCL IC1 IC11 IC9 TMS320VC5502 Fixed-Point Digital Signal Processor SPRS166H – APRIL 2001 – REVISED NOVEMBER 2004 Table 5-48 and Table 5-49 assume testing over recommended operating conditions (see Figure 5-47 and Figure 5-48). Table 5-48. I 2C Signals (SDA and SCL) Timing Requirements VC5502-200 VC5502-300 NO. Standard Fast UNIT Mode Mode MIN MAX MIN MAX IC1 tc(SCL) Cycle time, SCL 10 2.5 µs Setup time, SCL high before SDA low for a repeated START IC2 tsu(SCLH-SDAL) 4.7 0.6 µs condition Hold time, SCL low after SDA low for a START and a IC3 th(SCLL-SDAL) 4 0.6 µs repeated START condition IC4 tw(SCLL) Pulse duration, SCL low 4.7 1.3 µs IC5 tw(SCLH) Pulse duration, SCL high 4 0.6 µs IC6 tsu(SDA-SCLH) Setup time, SDA valid before SCL high 250 100(1) ns IC7 th(SDA-SCLL) Hold time, SDA valid after SCL low For I2C bus™ devices 0(2) 0(2) 0.9(3) µs Pulse duration, SDA high between STOP and START con- IC8 tw(SDAH) 4.7 1.3 µs ditions IC9 tr(SDA) Rise time, SDA 1000 20 + 0.1Cb(4) 300 ns IC10 tr(SCL) Rise time, SCL 1000 20 + 0.1Cb(4) 300 ns IC11 tf(SDA) Fall time, SDA 300 20 + 0.1Cb(4) 300 ns IC12 tf(SCL) Fall time, SCL 300 20 + 0.1Cb(4) 300 ns IC13 tsu(SCLH-SDAH) Setup time, SCL high before SDA high (for STOP condition) 4.0 0.6 µs IC14 tw(SP) Pulse duration, spike (must be suppressed) 0 50 ns IC15 Cb(4) Capacitive load for each bus line 400 400 pF (1) A Fast-mode I2C-bus device can be used in a Standard-mode I2C-bus system, but the requirement tsu(SDA-SCLH)≥ 250 ns must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line tr max + tsu(SDA-SCLH)= 1000 + 250 = 1250 ns (according to the Standard-mode I2C-Bus Specification) before the SCL line is released. (2) A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the VIHmin of the SCL signal) to bridge the undefined region of the falling edge of SCL. (3) The maximum th(SDA-SCLL) has only to be met if the 5502 I2C operates in master-receiver mode and the slave device does not stretch the LOW period [tw(SCLL)] of the SCL signal. (4) Cb = total capacitance of one bus line in pF. If mixed with HS-mode devices, faster fall-times are allowed. Figure 5-47. I2C Receive Timings Specifications 179 |
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