TSB43AB21 datasheet(36/109 Pages) TI

36 / 109 page

3–15

3.20 Power Management Control and Status Register

The power management control and status register implements the control and status of the PCI power management

function. This register is not affected by the internally generated reset caused by the transition from the D3hot to D0

state. See Table 3–18 for a complete description of the register contents.

Bit

Name

Power management control and status

Type

RWC

R/W

Default

Power management control and status

Offset:

48h

Type:

Read/Clear, Read/Write, Read-only

Default:

0000h

Table 3–18. Power Management Control and Status Register Description

BIT

FIELD NAME

TYPE

DESCRIPTION

PME_STS

RWC

Bit 15 is set to 1 when the TSB43AB21 device normally asserts the PCI_PME signal independent of

the state of bit 8 (PME_ENB). This bit is cleared by a writeback of 1, which also clears the PCI_PME

signal driven by the TSB43AB21 device. Writing a 0 to this bit has no effect.

14–13

DATA_SCALE

This field returns 0s, because the data register is not implemented.

12–9

DATA_SELECT

This field returns 0s, because the data register is not implemented.

PME_ENB

R/W

When bit 8 is set to 1, PME assertion is enabled. When bit 8 is cleared, PME assertion is disabled. This

bit defaults to 0 if the function does not support PME generation from D3cold. If the function supports

PME from D3cold, this bit is sticky and must be explicitly cleared by the operating system each time

it is initially loaded.

7–2

RSVD

Reserved. Bits 7–2 return 0s when read.

1–0

PWR_STATE

R/W

Power state. This 2-bit field sets the TSB43AB21 device power state and is encoded as follows:

00 = Current power state is D0.

01 = Current power state is D1.

10 = Current power state is D2.

11 = Current power state is D3.

3.21 Power Management Extension Registers

The power management extension register provides extended power-management features not applicable to the

TSB43AB21 device; thus, it is read-only and returns 0 when read. See Table 3–19 for a complete description of the

Bit

Name

Power management extension

Type

Default

Power management extension

Offset:

4Ah

Type:

Read-only

Default:

0000h

Table 3–19. Power Management Extension Registers Description

BIT

FIELD NAME

TYPE

DESCRIPTION

15–0

RSVD

Reserved. Bits 15–0 return 0s when read.

TSB43AB21 Datasheet(PDF) 36 Page - Texas Instruments

TSB43AB21 Datasheet(HTML) 36 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL