TSB43AB21 datasheet(71/109 Pages) TI

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4–30

4.34 Isochronous Cycle Timer Register

The isochronous cycle timer register indicates the current cycle number and offset. When the TSB43AB21 device

is cycle master, this register is transmitted with the cycle start message. When the TSB43AB21 device is not cycle

master, this register is loaded with the data field in an incoming cycle start. In the event that the cycle start message

is not received, the fields can continue incrementing on their own (if programmed) to maintain a local time reference.

See Table 4–26 for a complete description of the register contents.

Bit

Name

Isochronous cycle timer

Type

RWU

Default

Bit

Name

Isochronous cycle timer

Type

RWU

Default

Isochronous cycle timer

Offset:

F0h

Type:

Read/Write/Update

Default:

XXXX XXXXh

Table 4–26. Isochronous Cycle Timer Register Description

BIT

FIELD NAME

TYPE

DESCRIPTION

31–25

cycleSeconds

RWU

This field counts seconds [rollovers from bits 24–12 (cycleCount field)] modulo 128.

24–12

cycleCount

RWU

This field counts cycles [rollovers from bits 11–0 (cycleOffset field)] modulo 8000.

11–0

cycleOffset

RWU

This field counts 24.576-MHz clocks modulo 3072, that is, 125

µs. If an external 8-kHz clock

configuration is being used, this field must be cleared to 0s at each tick of the external clock.

TSB43AB21 Datasheet(PDF) 71 Page - Texas Instruments

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