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TSB43AB21 Datasheet(PDF) 89 Page - Texas Instruments |
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TSB43AB21 Datasheet(HTML) 89 Page - Texas Instruments |
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89 / 109 page  5–5 Table 5–3. Link Enhancement Register Description (Continued) 7 enab_unfair RSC Enable asynchronous priority requests. iOHCI-Lynx compatible. Setting bit 7 to 1 enables the link to respond to requests with priority arbitration. It is recommended that this bit be set to 1. 6 RSVD R This bit is not assigned in the TSB43AB21 follow-on products, since this bit location loaded by the serial EEPROM from the enhancements field corresponds to bit 23 (programPhyEnable) in the host controller control register at OHCI offset 50h/54h (see Section 4.16, Host Controller Control Register). 5–2 RSVD R Reserved. Bits 5–2 return 0s when read. 1 enab_accel RSC Enable acceleration enhancements. iOHCI-Lynx compatible. When bit 1 is set to 1, the PHY layer is notified that the link supports the IEEE Std 1394a-2000 acceleration enhancements, that is, ack-accelerated, fly-by concatenation, etc. It is recommended that this bit be set to 1. 0 RSVD R Reserved. Bit 0 returns 0 when read. 5.5 Timestamp Offset Register The value of this register is added as an offset to the cycle timer value when using the MPEG, DV, and CIP enhancements. A timestamp offset register is implemented per isochronous transmit context. The n value following the offset indicates the context number (n = 0, 1, 2, 3, …, 7). These registers are programmed by software as appropriate. See Table 5–4 for a complete description of the register contents. Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Name Timestamp offset Type R/W R R R R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name Timestamp offset Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Register: Timestamp offset Offset: A90h + (4*n) Type: Read/Write, read-only Default: 0000 0000h Table 5–4. Timestamp Offset Register Description BIT FIELD NAME TYPE DESCRIPTION 31 DisableInitialOffset R/W Bit 31 disables the use of the initial timestamp offset when the MPEG2 enhancements are enabled. A value of 0 indicates the use of the initial offset, a value of 1 indicates that the initial offset must not be applied to the calculated timestamp. This bit has no meaning for the DV timestamp enhancements. 30–25 RSVD R Reserved. Bits 30–25 return 0s when read. 24–12 CycleCount R/W This field adds an offset to the cycle count field in the timestamp when the DV or MPEG2 enhancements are enabled. The cycle count field is incremented modulo 8000; therefore, values in this field must be limited between 0 and 7999. 11–0 CycleOffset R/W This field adds an offset to the cycle offset field in the timestamp when the DV or MPEG2 enhancements are enabled. The cycle offset field is incremented modulo 3072; therefore, values in this field must be limited between 0 and 3071. |
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