TSB43AB21 datasheet(31/109 Pages) TI

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3–10

3.12 CardBus CIS Pointer Register

CARDBUS to the TSB43AB21 device is sampled at G_RST to determine the TSB43AB21 application. If CARDBUS

is sampled high, this register is read-only returning 0s when read. If CARDBUS is sampled low, this register contains

the pointer to the CardBus card information structure (CIS). See Table 3–11 for a complete description of the register

contents.

Bit

Name

CardBus CIS pointer

Type

Default

Bit

Name

CardBus CIS pointer

Type

Default

CardBus CIS pointer

Offset:

28h

Type:

Read-only

Default:

0000 0000h

Table 3–11. CardBus CIS Pointer Register Description

BIT

FIELD NAME

TYPE

DESCRIPTION

31–28

ROM_IMAGE

Since the CIS is not implemented as a ROM image, this field returns 0s when read.

27–3

CIS_OFFSET

This field indicates the offset into the CIS address space where the CIS begins, and bits 7–3 are

loaded from the serial EEPROM field CIS_Offset (7–3). This implementation allows the TSB43AB21

device to produce serial EEPROM addresses equal to the lower PCI address byte to acquire data

from the serial EEPROM.

2–0

CIS_INDICATOR

This field indicates the address space where the CIS resides and returns 011b if CARDBUS is

sampled low at G_RST. 011b indicates that CardBus CIS base address register at offset 18h in the

PCI configuration header contains the CIS base address. If CARDBUS is sampled high at G_RST,

this field contains 000b.

TSB43AB21 Datasheet(PDF) 31 Page - Texas Instruments

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