TSB43AB21 datasheet(33/109 Pages) TI

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3–12

3.15 Interrupt Line and Pin Register

The interrupt line and pin register communicates interrupt line routing information. See Table 3–13 for a complete

description of the register contents.

Bit

Name

Interrupt line and pin

Type

R/W

Default

Interrupt line and pin

Offset:

3Ch

Type:

Read/Write

Default:

0100h

Table 3–13. Interrupt Line and Pin Registers Description

BIT

FIELD NAME

TYPE

DESCRIPTION

15–8

INTR_PIN

Interrupt pin. This field returns 01h when read, indicating that the TSB43AB21 PCI function signals

interrupts on the PCI_INTA terminal.

7–0

INTR_LINE

R/W

Interrupt line. This field is programmed by the system and indicates to software which interrupt line the

TSB43AB21 PCI_INTA is connected to.

3.16 MIN_GNT and MAX_LAT Register

The MIN_GNT and MAX_LAT register communicates to the system the desired setting of bits 15–8 in the latency timer

and class cache line size register at offset 0Ch in the PCI configuration space (see Section 3.7, Latency Timer and

Class Cache Line Size Register). If a serial EEPROM is detected, the contents of this register are loaded through

the serial EEPROM interface after a G_RST. If no serial EEPROM is detected, this register returns a default value

that corresponds to the MAX_LAT = 4, MIN_GNT = 2. See Table 3–14 for a complete description of the register

contents.

Bit

Name

MIN_GNT and MAX_LAT

Type

Default

MIN_GNT and MAX_LAT

Offset:

3Eh

Type:

Read/Update

Default:

0402h

Table 3–14. MIN_GNT and MAX_LAT Register Description

BIT

FIELD NAME

TYPE

DESCRIPTION

15–8

MAX_LAT

Maximum latency. The contents of this field may be used by host BIOS to assign an arbitration priority level

to the TSB43AB21 device. The default for this register indicates that the TSB43AB21 device may need to

access the PCI bus as often as every 0.25

µs; thus, an extremely high priority level is requested. The

contents of this field may also be loaded through the serial EEPROM.

7–0

MIN_GNT

Minimum grant. The contents of this field may be used by host BIOS to assign a latency timer register value

to the TSB43AB21 device. The default for this register indicates that the TSB43AB21 device may need to

sustain burst transfers for nearly 64

µs and thus request a large value be programmed in bits 15–8 of the

TSB43AB21 latency timer and class cache line size register at offset 0Ch in the PCI configuration space

(see Section 3.7, Latency Timer and Class Cache Line Size Register).

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