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MCP19124 Datasheet(PDF) 228 Page - Microchip Technology |
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MCP19124 Datasheet(HTML) 228 Page - Microchip Technology |
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228 / 236 page  MCP19124/5 DS20005619A-page 228 2016 Microchip Technology Inc. D Data Memory Core Registers 71 STATUS Register 71 General Purpose Registers 70 Map 73 Organization 70 Special Function Registers 70 , 72 DC and AC Characteristics 53 Graphs and Tables 53 DEADCON Register 47 DESATCON Register 43 Desaturation Detection for Quasi-Resonant Operation 43 Development Support 213 Device Calibration 59 CALWD1 (Calibration Word 1) 59 CALWD10 (Calibration Word 10) 66 CALWD11 (Calibration Word 11) 67 , 68 CALWD2 (Calibration Word 2) 60 CALWD3 (Calibration Word 3) 61 CALWD4 (Calibration Word 4) 61 CALWD5 (Calibration Word 5) 62 CALWD6 (Calibration Word 6) 62 CALWD7 (Calibration Word 7) 63 CALWD8 (Calibration Word 8) 64 CALWD9 (Calibration Word 9) 65 Device Configuration 39 , 81 Code Protection 82 Configuration Word 81 ID Locations 82 Write Protection 82 Device Overview 9 Digital Electrical Characteristics 31 Direct Addressing 80 Driver Control Circuitry 20 E Electrical Characteristics 22 Errata 7 External Clock Timing 32 Timing Requirements 32 F Features 1 Microcontroller 1 Timer0 Module 137 Timer1 Module 139 File Select Register. See FSR Firmware Instructions 201 Flash Program Memory Control 131 Operation During Code Protect 135 Operation During Write Protect 135 Protection Against Spurious Write 135 Registers 132 Reading 134 Writing to 135 FSR Register 79 G General Purpose Register. See GPR GPR Register 70 I I/O Ports 107 I2C Mode (MSSP) Acknowledge Sequence 162 Acknowledge Sequence Timing 185 Associated Registers 191 Bus Collision During a Repeated Start Condition 189 During a Start Condition 187 During a Stop Condition 190 Effects of a Reset 186 I2C Clock Rate w/BRG 192 Master Mode 178 Clock Arbitration 178 Operation 178 Reception 183 Repeated Start Condition Timing 180 Start Condition Timing 179 Transmission 181 Multi-Master Communication, Bus Collision and Arbitra- tion 186 Multi-Master Mode 186 Operation 160 Overview 158 Read/Write Bit Information (R/W Bit) 162 Slave Mode 10-bit Address Reception 172 Bus Collision 168 Clock Stretching 176 Clock Synchronization 176 General Call Address Support 177 Operation 162 SSPMSK1 Register 177 Transmission 168 Sleep Operation 186 Stop Condition Timing 185 ICLEBCON Register 45 ICOACON Register 44 In-Circuit Serial Programming (ICSP) 211 Common Programming Interfaces 211 INDF Register 79 Indirect Addressing 79 , 80 Input 22 Overvoltage Lockout 39 Type 13 Undervoltage Lockout 39 Instruction Format 201 Instruction Set 201 ADDLW 203 ADDWF 203 ANDLW 203 ANDWF 203 BCF 203 BSF 203 BTFSC 203 BTFSS 204 CALL 204 CLRF 204 CLRW 204 CLRWDT 204 COMF 204 DECF 204 DECFSZ 205 |
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