MCP19124 datasheet(120/236 Pages) MICROCHIP

120 / 236 page

MCP19124/5

DS20005619A-page 120

 2016 Microchip Technology Inc.

19.1

ADC Configuration

When configuring and using the ADC, the following

functions must be considered:

• Port configuration

• Channel selection

• ADC conversion clock source

• Interrupt control

• Result formatting

19.1.1

PORT CONFIGURATION

The ADC is used to convert analog signals into a

corresponding digital representation. When converting

analog signals, the I/O pin should be configured for

analog by setting the associated TRIS and ANSEL bits.

Refer to Section 17.0 “I/O Ports” for more

information.

19.1.2

CHANNEL SELECTION

There are up to 21 channel selections available for the

MCP19124 and 24 channels for the MCP19125:

• AN<4:0> pins

• AN<7:5> pins (MCP19125 only)

•VIN: 1/15.53 of the input voltage (VIN)

•VREF: voltage reference for regulation set point

•OVREF: reference for OV comparator

•VBGR: band gap reference

•VS: voltage proportional to VOUT

• EA_SC: error amplifier output after slope

compensation

• A2: secondary current sense amplifier output

• Pedestal

• Reserved

• IP_ADJ: IP after pedestal and offset adjust

• IP_OFF_REF: IP offset reference

•VDR: VDR x 0.229V/V

• TEMP_SNS: analog voltage representing internal

temperature (refer to Equation 25-1)

• DLL_VCON: delay locked loop voltage reference

• SLPCMP_REF: slope compensation reference

The CHS<4:0> bits in the ADCON0 register determine

which channel is connected to the sample-and-hold

circuit.

When changing channels, a delay is required before

starting the next conversion. Refer to Section 19.2

“ADC Operation” for more information.

19.1.3

ADC CONVERSION CLOCK

The source of the conversion clock is software

selectable via the ADCS bits in the ADCON1 register.

There are five possible clock options:

•FOSC/8

•FOSC/16

•FOSC/32

•FOSC/64

•FRC (clock derived from internal oscillator with a

divisor of 16)

The time to complete one-bit conversion is defined as

TAD. One full 10-bit conversion requires 11 TAD periods,

as shown in Figure 19-2.

For a correct conversion, the appropriate TAD

specification must be met. Refer to the A/D conversion

requirements

Section 4.0

“Electrical

Characteristics” for more information. Table 19-1

gives examples of appropriate ADC clock selections.

Note:

Analog voltages on any pin that is defined

as a digital input may cause the input

buffer to conduct excess current.

Note:

Unless using the FRC, any changes in the

system clock frequency will change the

ADC

clock

frequency,

which

may

adversely affect the ADC result.

TABLE 19-1:

ADC CLOCK PERIOD (TAD) VS.

DEVICE OPERATING

FREQUENCIES

ADC Clock Period (TAD)

Device

Frequency

(FOSC)

ADC

Clock Source

ADCS<2:0>

8 MHz

FOSC/8

001

1.0 µs (1)

FOSC/16

101

2.0 µs

FOSC/32

010

4.0 µs

FOSC/64

110

8.0 µs (2)

FRC

x11

2.0-6.0 µs (3, 4)

Legend: Shaded cells are outside of

recommended range.

Note 1: These values violate the minimum

required TAD time.

2: For faster conversion times, the selection

of another clock source is recommended.

3: The FRC source has a typical TAD time of

4 µs for VDD >3.0V.

4: The FRC clock source is only

recommended if the conversion will be

performed during Sleep.

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