DM505 datasheet(106/286 Pages) TI1

106 / 286 page

vssa_osc1

Device

xo_osc1

xi_osc1

SPRS91v_CLK_06

106

DM505

SPRS976A – NOVEMBER 2016 – REVISED JANUARY 2017

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Specifications

Figure 5-11. 1.8-V LVCMOS-Compatible Clock Input

Table 5-22 summarizes the OSC1 input clock electrical characteristics.

Table 5-22. OSC1 Input Clock Electrical Characteristics—Bypass Mode

NAME

DESCRIPTION

MIN

TYP

MAX

UNIT

Frequency

Range from 12 to 38.4

MHz

CIN

Input capacitance

2.819

3.019

3.219

IIN

Input current (3.3V mode)

µA

tsX

Start-up time(1)

See(2)

(1) To switch from bypass mode to crystal or from crystal mode to bypass mode, there is a waiting time about 100 μs; however, if the chip

comes from bypass mode to crystal mode the crystal will start-up after time mentioned in Table 5-21, tsX parameter.

(2) Before the processor boots up and the oscillator is set to bypass mode, there is a waiting time when the internal oscillator is in

application mode and receives a wave. The switching time in this case is about 100 μs.

Table 5-23 details the OSC1 input clock timing requirements.

Table 5-23. OSC1 Input Clock Timing Requirements

NAME

DESCRIPTION

MIN

TYP

MAX

UNIT

CK0

1 / tc(xiosc1)

Frequency, xi_osc1

Range from 12 to 38.4

MHz

CK1

tw(xiosc1)

Pulse duration, xi_osc1 low or high

0.45 × tc(xiosc1)

0.55 × tc(xiosc1)

tj(xiosc1)

Period jitter(1), xi_osc1

0.01 × tc(xiosc1)

(3)

tR(xiosc1)

Rise time, xi_osc1

tF(xiosc1)

Fall time, xi_osc1

tj(xiosc1)

Frequency accuracy(2), xi_osc1

Ethernet not used

±200

ppm

Ethernet RGMII using

derived clock

±50

ppm

(1) Period jitter is meant here as follows:

– The maximum value is the difference between the longest measured clock period and the expected clock period

– The minimum value is the difference between the shortest measured clock period and the expected clock period

(2) Crystal characteristics should account for tolerance+stability+aging.

(3) The Period jitter requirement for osc1 can be relaxed to 0.02*tc(xiosc1) under the following constraints:

a. The osc1/SYS_CLK2 clock bypasses all device PLLs

b. The osc1/SYS_CLK2 clock is only used to source the DSS pixel clock outputs

DM505 Datasheet(PDF) 106 Page - Texas Instruments

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