LPC18S50 datasheet(112/151 Pages) NXP

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LPC18S50_S30_S10

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Product data sheet

Rev. 1 — 23 February 2015

112 of 151

NXP Semiconductors

LPC18S50/S30/S10

32-bit ARM Cortex-M3 microcontroller

delay time

continuous transfer mode

SPI mode; CPOL = 0;

CPHA = 0

0.5 Tcy(clk)

SPI mode; CPOL = 0;

CPHA = 1

-n/a

SPI mode; CPOL = 1;

CPHA = 0

0.5 Tcy(clk)

SPI mode; CPOL = 1;

CPHA = 1

-n/a

synchronous serial

frame mode

-Tcy(clk)

microwire frame format

n/a

SSP slave

Tcy(PCLK)

PCLK cycle time

Tcy(clk)

clock cycle time

[2]

120

tDS

data set-up time

in SPI mode

1.2

tDH

data hold time

in SPI mode

0.5

tv(Q)

data output valid

time

in SPI mode

17.7

th(Q)

data output hold

time

in SPI mode

5.1

tlead

lead time

continuous transfer mode

SPI mode; CPOL = 0;

CPHA = 0

Tcy(clk) + 2.2

SPI mode; CPOL = 0;

CPHA = 1

0.5Tcy(clk) + 2.2

SPI mode; CPOL = 1;

CPHA = 0

Tcy(clk) + 2.2

SPI mode; CPOL = 1;

CPHA = 1

0.5Tcy(clk) + 2.2

synchronous serial

frame mode

0.5Tcy(clk) + 2.2

microwire frame format

Tcy(clk) + 2.2

Table 22.

Dynamic characteristics: SSP pins in SPI mode

Tamb = 40 C to +85 C; 2.2 V  VDD(REG)(3V3)  3.6 V; 2.7 V  VDD(IO)  3.6 V; CL = 20 pF. Sampled at 10 % and 90 % of the

signal level; EHS = 1 for all pins. Simulated values.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

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