LPC18S50 datasheet(113/151 Pages) NXP

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LPC18S50_S30_S10

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Product data sheet

Rev. 1 — 23 February 2015

113 of 151

NXP Semiconductors

LPC18S50/S30/S10

32-bit ARM Cortex-M3 microcontroller

[1]

Tcy(clk) = (SSPCLKDIV  (1 + SCR)  CPSDVSR) / fmain. The clock cycle time derived from the SPI bit rate Tcy(clk) is a function of the

main clock frequency fmain, the SSP peripheral clock divider (SSPCLKDIV), the SSP SCR parameter (specified in the SSP0CR0

[2]

Tcy(clk) = 12  Tcy(PCLK).

tlag

lag time

continuous transfer mode

SPI mode; CPOL = 0;

CPHA = 0

0.5Tcy(clk) + 0.2

SPI mode; CPOL = 0;

CPHA = 1

Tcy(clk) + 0.2

SPI mode; CPOL = 1;

CPHA = 0

0.5Tcy(clk) + 0.2

SPI mode; CPOL = 1;

CPHA = 1

Tcy(clk) + 0.2

synchronous serial

frame mode

Tcy(clk) + 0.2

microwire frame format

0.5Tcy(clk)

delay time

continuous transfer mode

SPI mode; CPOL = 0;

CPHA = 0

0.5 Tcy(clk)

SPI mode; CPOL = 0;

CPHA = 1

-n/a

SPI mode; CPOL = 1;

CPHA = 0

0.5 Tcy(clk)

SPI mode; CPOL = 1;

CPHA = 1

-n/a

synchronous serial

frame mode

-Tcy(clk)

microwire frame format

n/a

Table 22.

Dynamic characteristics: SSP pins in SPI mode

Tamb = 40 C to +85 C; 2.2 V  VDD(REG)(3V3)  3.6 V; 2.7 V  VDD(IO)  3.6 V; CL = 20 pF. Sampled at 10 % and 90 % of the

signal level; EHS = 1 for all pins. Simulated values.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

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