PC87306 datasheet(24/110 Pages) NSC

24 / 110 page

20 Configuration Registers (Continued)

Bit 2

EPP Timeout Interrupt Enable bit

When this bit is 0 the EPP timeout interrupt is

masked

When this bit is 1 the EPP timeout interrupt is

generated on the selected IRQ line (IRQ5 or

IRQ7) according to bits 46 of PCR

Bits 3 – 7

Reserved

259 SuperIO Identification Register

(SID Index e 08h)

The SID Register is accessed like the other configuration

registers through the Index Register This read-only register

is used to identify the PC87306 chip

TLC12379 – 27

2510 Advanced SuperIO Configuration Register

(ASC Index e 09h)

During reset bits 0 – 2 and bit 5 are initialzed to 0 and bits 6 –

7 are initialized to 1

Bit 0 1

VLD0 1 These bits determine the state of bit 5

in the FDC Tape Drive Register (TDR) when ei-

ther Automatic Media Sense TDR or Enhanced

TDR is configured (FCR0 e 0 or ASC2 e 1) For

more details see the TDR description

Bit 2

Enhanced TDR support

0 PC-AT Compatible TDR or Automatic Media

Sense TDR selected by FCR0

1 Enhanced TDR

Bit 3

Reserved bit On ASC writes this bit must be

written with a 0 On ASC reads the value is un-

defined

Bit 4

Reserved

Bit 5

The value of this pin is reflected on bit 3 of

CNFGA ECP register

Bit 6

DENSEL’s polarity control bit

0 DENSEL is active low for 500 kbps or 1 Mbps

data rates

1 DENSEL is active high for 500 kbps or 1 Mbps

data rates

Bit 7

System Operation Mode The PC87306 can be

configured to either PC-AT or PS2 modes

0 PS2 mode

1 PC-AT mode

Upon reset this bit is initialized to 1 thus select-

ing PC-AT mode

2511 Chip Select 0 Low Address (CS0LA Index e 0Ah)

This register holds the low address bits of the monitored IO

address Bit 0 holds A0 Upon reset this register is set to 0

See CS0CF for a description of CS0 enable on read and

write cycles

2512 Chip Select 0 High Address (CS0HA Index e

10h)

This register holds the high address bits of the monitored

IO address Bit 0 holds A8 Upon reset this register is set to

See CS0CF for a description of CS0 enable on read and

write cycles

2513 Chip Select 0 Configuration Register (CS0CF

Index e 0Bh)

This register controls the behavior of the CS0 pin CS0 is

asserted on non-DMA PIO cycles when RD or WR is as-

serted CS0 can be asserted three ways 1) only on reads

2) only on writes or 3) on all cycles The register is initialized

to 1X000XXX during reset

Bits 0 – 2

Reserved

Bit 3

Chip Select 0 Decode

0 Decode 16-bit

1 Decode address bits 15 – 12 (HA15 – HA12 of

CS0HA) and CS0LA are ignored

Bit 4

0 Disable CS0 assertion on write cycles

1 Enable CS0 assertion on write cycles

Bit 5

0 Disable CS0 assertion on read cycles

1 Enable CS0 assertion on read cycles

Bit 6

Reserved

Bit 7

CS0 pin enable

0 Reserved for National use

1 CS0 pin is enabled

2514 Chip Select 1 Low Address (CS1LA Index e 0Ch)

This register holds the low address bits of the monitored IO

address Bit 0 holds A0 Upon reset this register is set to 0

See CS1CF for a description of CS1 enable on read and

write cycles

2515 Chip Select 1 High Address (CS1HA Index e

11h)

This register holds the high address bits of the monitored

IO address Bit 0 holds A8 Upon reset this register is set to

See CS1CF for a description of CS1 enable on read and

write cycles

2516 Chip Select 1 Configuration Register (CS1CF

Index e 0Dh)

This register controls the behavior of the CS1 pin CS1 is

asserted on non-DMA PIO cycles when RD or WR is as-

serted CS1 can be asserted three ways 1) only on reads

2) only on writes or 3) on all cycles The register is initialized

to XX00XXXX during reset

Bits 0 – 2

Reserved

Bit 3

Chip Select Decode

0 Decode 16-bit (CS1LA and CS1HA)

1 Decode address bits 15 – 2 CS1LA bits 0 and

1 are ignored

Bit 4

Enable CS1 assertion on write cycles

Bit 5

Enable CS1 assertion on read cycles

Bits 6 – 7

Reserved

2517 InfraRed Configuration Register (IRC Index e

0Eh)

After reset the register holds the value XX00XX00

Bit 0

UART2 Interface Mode This bit is used for run time

selection of either Normal (MODEM) Mode or IR

Mode

0 Normal (MODEM) Mode

1 InfraRed (IR) Mode

Bit 1

IR HalfFull Duplex configuration bit

0 Full Duplex Both transmitter and receiver are en-

abled simultaneously

PC87306 Datasheet(PDF) 24 Page - National Semiconductor (TI)

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