PC87306 datasheet(22/110 Pages) NSC

22 / 110 page

20 Configuration Registers (Continued)

TABLE 2-10 TRI-STATE Conditions of IRQ3 and IRQ4

Bit 0 of PNP1 e 0

Bit 0 of PNP1 e 1

IRQ3

According to FAR

(PNP1bit2 e 1) or

selection and

(FERbit1 e 0) or

bits 3 4 of MCR

(MCR1bit3 e 0) or

(MCR1bit4 e 1)

and

(PNP1bit6 e 1) or

(FERbit2 e 0) or

(MCR2bit3 e 0) or

(MCR2bit4 e 1)

IRQ4

According to FAR

(PNP1bit2 e 0) or

selection and

(FERbit1 e 0) or

bits 3 4 of MCR

(MCR1bit3 e 0) or

(MCR1bit4 e 1)

and

(PNP1bit6 e 0) or

(FERbit2 e 0) or

(MCR2bit3 e 0) or

(MCR2bit4 e 1)

253 Power and Test Register (PTR Index e 02h)

This register determines several power-down features the

power-down method used when the power-down pin

(PWDN) is asserted (crystal and clocks vs clocks only)

whether hardware power-down is enabled and provides a

bit for software power-down of all enabled functions It se-

lects whether IRQ7 or IRQ5 is associated with LPTB It puts

the enabled UARTs into their test mode See Table 2-1 for

its reset value

Independent of this register the floppy disk controller can

enter low power mode via the Mode Command or the Data

Rate Select Register

Bit 0

Setting this bit causes all enabled functions to be

powered down

Bit 1

Reserved

Bit 2

Reserved

Bit 3

Setting this bit associates the parallel port with IRQ7

when the address for the parallel port is 378 – 37Fh

(LPTB) This bit is a ‘‘don’t care’’ when the parallel

port address is 3BC – 3BEh (LPTA) or 278 – 27Fh

(LPTC)

When bit 4 of PNP0 is 1 this bit is ignored

Bit 4

Setting this bit puts UART1 into a test mode which

causes its Baud Out clock to be present on its SOUT1

pin if the Line Control Register bit 7 is set to 1

Bit 5

Setting this bit puts UART2 into a test mode which

causes its Baud Out clock to be present on its SOUT2

pin if the Line Control Register bit 7 is set to 1

Bit 6

Setting this bit to a 1 prevents all further write access-

es to the Configuration Registers Once it is set by

software it can only be cleared by a hardware reset

Bit 7

When not in EPP or ECP modes this bit controls

CompatibleExtended mode thus controlling Pulse

Level interrupt

Set this bit to 0 for Compatible mode Pulse Inter-

rupt Set this bit to 1 for Extended mode Level In-

terrupt

Note

Parallel port interrupt (PulseLevel) in EPP and ECP

modes is always pulse

This bit is ignored in ECP and EPP modes

254 Function Control Register (FCR Index e 03h)

This register enables the ZWS option when in Enhanced

Parallel Port mode

On reset the FCR is initialized to X00XXX01

Bit 0

TDR Mode Select bit This bit selects the TDR

mode when ASC2 e 0 as follows

0 Automatic Media Sense TDR (PC87322 type)

1 PC-AT Compatible TDR (PC87312 type)

This bit is ignored when ASC2 e 1 See ASC bit 2

for complete TDR mode selection

Bit 1

IDE DMA Enable Bit When this bit is 0 the IDE

DMA is disabled When this bit is 1 the IDE DMA is

enabled

Bit 2

Reserved

Bit 3

Reserved

Bit 4

Reserved

Bit 5

Zero Wait State enable bit If this bit is 1 ZWS is

driven low when the Enhanced Parallel Port

(EPP) or the ECP can accept a short host read

write-cycle otherwise the ZWS open drain output

is not driven EPP ZWS operation should be con-

figured when the system’s device is fast enough

to support it

Bits 6 7

Reserved Use Read Modified Write to change the

FCR register

255 Printer Control Register (PCR Index e 04h)

This register enables the EPP and ECP version modes and

interrupt options It also enables the RTC RAM write mask

bit On reset the PCR bits are cleared to 0

The parallel port mode is software configurable as shown in

Table 2-11

TABLE 2-11 Parallel Port Mode

Operation

FER

PTR

PCR

Mode

Bit 0

Bit 7

Bit 0

Bit 2

None

Compatible

1000

Extended

1100

EPP

ECP

Bit 0

EPP enable bit When this bit is 0 the EPP is dis-

abled and the EPP registers are not accessible

(access ignored)

When this bit is 1 and bit 2 of PCR is 0 the EPP is

enabled Note that the EPP should not be config-

ured with base address 3BCh

For further information refer to bit 5 of FCR

Bit 1

EPP version select bit When this bit is 0 Version

17 is supported and STB AFD INIT and SLIN

are open drain outputs

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