PC87306 datasheet(12/110 Pages) NSC

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10 Pin Description (Continued)

TABLE 1-1 Pin Descriptions (Alphabetical)

(Continued)

Symbol

Function

HDSEL

FDC Head Select

This output determines which side of the FDD is accessed When Active the head

selects side 1 When inactive the head selects side 0

IDEACK

IDE DMA Acknowledge

This is the IDE DMA acknowledge input pin when bit 1 of FCR is 1

IDED7

IDE Bit 7

This pin provides the data bus bit 7 signal to the IDE hard drive during accesses in the

address range 1F0 – 1F7h 170 – 177h 3F6h and 376h This pin is TRI-STATE during read or write

accesses to 3F7h and 377h

IDEHI

IDE High Byte

This output enables the high byte data latch during a read or write to the hard drive if

the hard drive returns IOCS16 This output is inactive if the IDE interface is disabled via the

Configuration Register

IDELO

IDE Low Byte

This output enables the low byte data latch during a read or write to the hard drive This

output is inactive if the IDE interface is disabled via the Configuration Register (See CFG0 for further

information)

INDEX

FDC Index

This input signals the beginning of a FDD track

INIT

122

Initialize

When this signal is low it causes a connected printer to be initialized This pin is in a TRI-

STATE condition 10 ns aftera1is loaded into the corresponding Control Register bit The system

should pull this pin high using a 47 kX resistor

IOCHRDY

IO Channel Ready

This is the IO Channel Ready open drain output When IOCHRDY is driven low

the EPP extends the host cycle

IOCS16

IO Chip Select 16-Bit

This input is driven by a connected peripheral device which can accommodate

a 16-bit access This pin is configured when bit 2 of ASC is 0

IRRX

113

Infrared Receiver

IRTX

114

Infrared Transmitter

IRQ1

Interrupt 1

KBC’s keyboard interrupt generated from internal P24 of the KBC

IRQ3 4

19 18

Interrupt 3 and 4

These are active high interrupts associated with the serial ports When bit 0 of the

Plug and Play register (PNP1) is 0 IRQ3 presents the signal if the serial channel has been designated

as COM2 or COM4 and IRQ4 presents the signal if the serial port is designated as COM1 or COM3

The appropriate interrupt goes active whenever it is enabled via the Interrupt Enable Register (IER)

the associated Interrupt Enable bit (Modem Control Register bit 3 MCR3) and any of the following

conditions are active Receiver Error Receive Data available Transmitter Holding Register Empty or a

Modem Status Flag is set The interrupt signal is reset low (inactive) after the appropriate interrupt

service routine is executed after being disabled via the IER or after a Master Reset

Either interrupt can be disabled putting it into TRI-STATE by setting the MCR3 bit low When bit 0 of

the PNP1 register is 1 IRQ3 and IRQ4 are selected according to bits 2 amd 6 of the PNP1 register

See Table 2-10 for IRQ3 and IRQ4 TRI-STATE conditions

IRQ5

Interrupt 5

Active high output that indicates a parallel port interrupt When enabled this bit follows the

ACK signal input When bit 4 in the parallel port Control Register is set and the parallel port address is

designated as shown in Table 2-5 this interrupt is enabled When it is not enabled this signal is

TRI-STATE

This pin is IO only when ECP is enabled IRQ5 is configured and bit 6 of PCR is 1 When bit 4 of the

PNP0 register is 1 IRQ5 and IRQ7 are selected according to bit 5 of the PNP0 register See Table 2-9

for IRQ5 and IRQ7 TRI-STATE conditions

IRQ6

Interrupt 6

Active high output to signal the completion of the execution phase for certain FDC

commands Also used to signal when a data transfer is ready during a Non-DMA operation When in

PC-AT or Model 30 mode this signal is enabled by bit D3 of the DOR When in PS2 mode IRQ6 is

always enabled and bit D3 of the DOR is reserved

IRQ7

Interrupt 7

Active high output that indicates a parallel port interrupt When enabled this bit follows the

ACK signal input When bit 4 in the parallel port Control Register is set and the parallel port address is

designated as shown in Table 2-5 this interrupt is enabled When it is not enabled this signal is

TRI-STATE

This pin is IO only when ECP is enabled IRQ7 is configured and bit 6 of PCR is 1 For ECP operation

refer to the interrupt ECP Section 7111

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