PC87306 datasheet(72/110 Pages) NSC

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80 Parallel Port (Continued)

TABLE 8-5 EPP Register Addresses

Address

Access

Description

Data (DTR)

A write to this register sets the state of the eight data pins on the 25-pin D-

shell connector

Status (STR)

A read from this register presents the system microprocessor with the

real-time status of five pins on the 25-pin D-shell connector and the IRQ

Control (CTR)

A write operation to this port sets the state of four pins on the 25-pin D-

shell connector and controls both the parallel port interrupt enable and

direction

Address

A write operation to this port initiates an EPP deviceregister selection

operation

Data Port 0

Accesses to this port initiate device read or write operations with bits 0 – 7

Data Port 1

This port is only accessed to transfer bits 8 to 15 of a 16-bit read or write

to data port 0

Data Port 2

This port is only accessed to transfer bits 16 to 23 of a 32-bit read or write

to data port 0

Data Port 3

This port is only accessed to transfer bits 24 to 31 of a 32-bit read or write

to data port 0

There are two EPP modes

EPP rev 17 is supported when bit 0 of PCR is 1 and bit 1 of

PCR is 0

EPP rev 19 (IEEE 1284) is supported when bit 0 of PCR is

1 and bit 1 of PCR is 1

EPP is supported for a parallel port whose base address is

8-bytes aligned (A0 1 2 e 0 0 0) Otherwise unpredictable

results occur There are four EPP transfer operations ad-

dress write address read data write and data read An EPP

transfer operation is composed of a host read or write cycle

(from or to an EPP register) and an EPP read or write cycle

(from a peripheral device to an EPP register or from an EPP

The software must write zero to bits 0 1 and 3 of the CTR

controlled by these bits are controlled by hardware during

EPP access Once these bits are written with zero the soft-

ware may issue multiple EPP access cycles When EPP is

enabled the software should writea1tobit5of CTR

To meet the EPP 19 specifications the software should

write to DTR only when bit 7 of STR is 1

EPP 17 Address Write

The following procedure selects a peripheral device or reg-

ister See also

Figure 8-1

1 The host writes a byte to the EPP address register WR

goes low to latch D0 – D7 into the address register The

latch drives the address register onto PD0 – 7 and the

EPP pulls WRITE low

2 The EPP pulls ASTRB low to indicate that data has been

sent

3 If WAIT is low during the host write cycle IOCHRDY

goes low

When WAIT goes high the EPP pulls IOCHRDY high

4 When IOCHRDY goes high it causes WR to go high If

WAIT is high during the host write cycle then the EPP

does not pull IOCHRDY to low

5 When WR goes high it causes the EPP to pull WRITE

and ASTRB to high

Only when WRITE and ASTRB are high can the EPP

change PD0 – 7

TLC12379 – 42

FIGURE 8-1 EPP 17 Address Write

EPP 17 Address Read

The following procedure reads from the address register

PC87306 Datasheet(PDF) 72 Page - National Semiconductor (TI)

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