PC87306 datasheet(89/110 Pages) NSC

89 / 110 page

100 Keyboard Controller and Real-Time Clock (Continued)

1027 System Bus Lock Out and Power-Up Detection

As the RTC switches to battery power all inputs are locked

out so that the internal registers can not be modified This

lockout condition continues for 62 ms (min) to 125 ms (max)

after the RTC switches from battery power to system power

The 62 ms – 125 ms lockout during power transition from

battery to system power depends on the following condi-

tions

1 If the Divider Chain Control (bits 6 – 4 in Control Register

A) is in any mode but Normal Operation (010) all inputs

are enabled immediately upon detection of system volt-

age above that of battery voltage

2 When Battery voltage is below 1V and MR is 1 all inputs

are enabled immediately upon detection of system volt-

age above that of battery voltage This also initializes

registers 00 through 0D to 00

3 If the VRT bit (bit 7 in Control Register D) is 0 all inputs

are enabled immediately upon detection of system volt-

age above that of battery voltage

1028 Oscillator

When power is applied to the RTC in the PC87306 the

Oscillator is operational with the following exceptions

1 The VRT bit (bit 7 in Control Register D) is a 0 The

oscillator is disabled after initial power-up This reduces

power consumption during the time between when the

battery is initially installed and when the RTC is initialized

for timekeeping

2 The Divider Chain Control (bits 6 – 4 in Control Register

A) is in Oscillator Disabled modes (000 and 001) This

provides a means for the user to ‘‘shut-down’’ the oscil-

lator and reduce the power consumption of the RTC cell

The RAM remains functional when the oscillator is dis-

abled

1029 Interrupt Handling

The Periodic Alarm and Update ended Interrupts are gen-

erated (IRQZ is driven low) when the respective enable bits

in Control Register B are set and an interrupt condition oc-

curs A read from Register C clears the active interrupt If a

second interrupt condition occurs (other than that which

caused the interrupt) during a read from Register C IRQZ

remains active (low) Thus it is recommended that when

multiple interrupts are enabled the interrupt service routine

continues to read (and service interrupts) until bit 7 of Con-

trol Register C (IRQ Flag) returns to a 1 Note that if an

interrupt is not serviced before a second condition of the

same interrupt occurs the second interrupt event is lost

10210 Control Registers

The four Control Registers used to configure timing inter-

rupts can be accessed at any time during non-battery

backed operation These Control Registers are located at

addresses 0Ah 0Bh 0Ch and 0Dh Their descriptions fol-

low

Control Register A

UIP

DV2

DV1

DV0

RS3

RS2

RS1

RS0

bit

3210

Bits 0 – 3 RS3 – 0Periodic Interrupt Rate Select

(ReadWrite)

These bits control the rate of the periodic inter-

rupt Reset has no effect on these bits

RS3–0

Periodic

Interrupt Rate

0000

None

0001

390625

0010

78125

0011

122070

0100

244141

0101

488281

0110

976562

0111

1953125

1000

390625

1001

78125

1010

15625

1011

3125

1100

625

1101

125

1110

250

1111

500

Bits 4 – 6 DV2 – 0Divider Chain Control

(ReadWrite)

These bits control the configuration of the divider

chain in the Timing Generation function

Reset has no effect on these bits

DV2–0

Divider Chain

Configuration

000

Oscillator Disabled

001

Oscillator Disabled

010

Normal Operation

011

TEST

100

TEST

101

TEST

110

Divider Chain RESET

111

Divider Chain RESET

Bit 7

UIPUpdate in Progress

(Read Only)

1 Signifies that the timing registers will be up-

dated within 244 ms

0 Signifies that an update will not occur before

244 ms This bit reads 0 when bit 7 of Control

Reset has no effect on this bit

PC87306 Datasheet(PDF) 89 Page - National Semiconductor (TI)

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