PC87306 datasheet(63/110 Pages) NSC

63 / 110 page

60 Serial Ports

Each of these serial ports functions as a serial data input

output interface in a microcomputer system The system

software determines the functional configuration of the

UARTs via a 8-bit bidirectional data bus

The UARTs are completely independent They perform

serial-to-parallel conversion on data characters received

from a peripheral device or a MODEM and parallel-to-serial

conversion on data characters received from the CPU The

CPU can read the complete status of either UART at any

time during the functional operation Status information re-

ported includes the type and condition of the transfer opera-

tions being performed by the UART as well as any error

conditions (parity overrun framing or break interrupt)

The UARTs have programmable baud rate generators that

are capable of dividing the internal reference clock by divi-

sors of 1 to (216 – 1) and producing a 16x clock for driving

the transmitter logic Provisions are also included to use this

16x clock to drive the receiver logic The UARTs have com-

plete MODEM-control capability and a prioritized interrupt

system Interrupts can be programmed to the user’s require-

ments minimizing the computing required to handle the

communications link

61 SERIAL PORT REGISTERS

Two identical register sets one for each channel are in the

PC87306 All register descriptions in this section apply to

the register sets in both channels See Table 6-1

TABLE 6-1 PC87306 UART

DLAB

Selected Register

Receiver Buffer (Read)

Transmitter Holding (Write)

Interrupt Enable

Interrupt Identification (Read)

FIFO Control (Write)

Line Control

MODEM Control

Line Status

MODEM Status

Scratch

Divisor Latch

(Least Significant Byte)

Divisor Latch

(Most Significant Byte)

62 LINE CONTROL REGISTER (LCR)

ReadWrite

The system programmer uses the Line Control Register

(LCR) to specify the format of the asynchronous data com-

munications exchange and set the Divisor Latch Access bit

This is a read and write register Table 6-2 shows the con-

tents of the LCR Details on each bit follow

TLC12379 – 37

FIGURE 6-1 PC87306 Composite Serial Data

Bits 01

These two bits specify the number of data bits in

each transmitted or received serial character The

encoding of bits 0 and 1 is as follows

Bit 1

Bit 0

Data Length

5 Bits

6 Bits

7 Bits

8 Bits

Bit 2

This bit specifies the number of Stop bits transmit-

ted with each serial character If it is 0 one Stop

bit is generated in the transmitted data If it is 1

when a 5-bit data length is selected one and a

half Stop bits are generated If it is logic 1 when

either a 6- 7- or 8-bit word length is selected two

Stop bits are generated The receiver checks the

first Stop bit only regardless of the number of

Stop bits selected

Bit 3

This bit is the Parity Enable bit When it is 1 a

Parity bit is generated (transmit data) or checked

(receive data) between the last data bit and Stop

bit of the serial data (The Parity bit is used to

produce an even or odd number of 1s when the

data bits and the Parity bit are summed)

Bit 4

This bit is the Even Parity Select bit When parity is

enabled and bit 4 is 0 an odd number of logic 1s

is transmitted or checked in the data word bits and

Parity bit When parity is enabled and bit 4 is 1 an

even number of logic 1s is transmitted or checked

Bit 5

This bit is the Stick Parity bit When parity is en-

abled it is used in conjunction with bit 4 to select

Mark or Space Parity When LCR bits 3 4 and 5

are 1 the Parity bit is transmitted and checked as a

0 (Space Parity) If bits 3 and 5 are 1 and bit 4 is a

0 then the Parity bit is transmitted and checked as

1 (Mark Parity) If bit 5 is 0 Stick Parity is disabled

Bit 6

This bit is the Break Control bit It causes a break

condition to be transmitted to the receiving UART

When it is set to 1 the serial output (SOUT) is

forced to the Spacing state (0) The break is dis-

abled by setting bit 6 to 0 The Break Control bit

acts only on SOUT and has no effect on the trans-

mitter logic

Note that this feature enables the CPU to alert a

terminal If the following sequence is used no er-

roneous characters will be transmitted because of

the break

1 Wait for the transmitter to be idle (TEMT e 1)

2 Set break for the appropriate amount of time If

the transmitter will be used to time the break

duration then check that TEMT e 1 before

clearing the Break Control bit

3 Clear break when normal transmission has to

be restored

During the break the Transmitter can be used as

a character timer to accurately establish the break

duration by sending characters and monitoring

THRE and TEMT

PC87306 Datasheet(PDF) 63 Page - National Semiconductor (TI)

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