PC87306 datasheet(68/110 Pages) NSC

68 / 110 page

60 Serial Ports (Continued)

TABLE 6-5 PC87306 Interrupt Control Functions

Interrupt

Interrupt Set and Reset Functions

Identification

Bit 3

Bit 2

Bit 1

Bit 0

Priority

Level

Interrupt Type

Interrupt Source

Interrupt Reset

Control

(FIFO

Mode

Only)

None

Highest

Receiver Line

Overrun Error Parity Error

Reading the Line

Status

Framing Error or Break Interrupt

Status Register

Second

Received Data

Receiver Data Available

Read Receiver Buffer

Available

Second

Character

No Characters Have Been

Reading the Receiver

(FIFO

Time-Out

Removed from or input to the

Buffer Register

Mode

Indication

RCVR FIFO During the Last 4

Only)

Character Times and there is at

least 1 Character in it during this

Time

Third

Transmitter Holding

Reading the IIR Register

(if Source of Interrupt) or

Writing the Transmitter

Holding Register

Fourth

MODEM Status

Clear to Send or Data Set

Reading the MODEM

Ready or Ring Indicator or

Status Register

Data Carrier Detect

69 MODEM STATUS REGISTER (MSR)

This register provides the current state of the control lines

from the MODEM (or peripheral device) to the CPU In addi-

tion to this current-state information

four bits of the

MODEM Status Register provide change information These

bits are set to a logic 1 whenever a control input from the

MODEM changes state They are reset to logic 0 whenever

the CPU reads the MODEM Status Register Table 6-2

shows the contents of the MSR Details on each bit follow

Bit 0

This bit is the Delta Clear to Send (DCTS) indicator

Bit 0 indicates that the CTS input to the chip has

changed state since the last time it was read by the

CPU

Bit 1

This bit is the Delta Data Set Ready (DDSR) indica-

tor It indicates that the DSR input to the chip has

changed state since the last time it was read by the

CPU

Bit 2

This bit is the Trailing Edge of Ring Indicator (TERI)

detector It indicates that the RI input to the chip has

changed from a low to a high state

Bit 3

This bit is the Delta Data Carrier Detect (DDCD) in-

dicator It indicates that the DCD input to the chip

has changed state

Note

Whenever bit 0 1 2 or 3 is set to logic 1 a MODEM Status

Interrupt is generated

Bit 4

This bit is the complement of the Clear to Send

(CTS) input If bit 4 (loopback) of the MCR is set to a

1 this bit is equivalent to RTS in the MCR

Bit 5

This bit is the complement of the Data Set Ready

(DSR) input If bit 4 of the MCR is set to a 1 this bit

is equivalent to DTR in the MCR

Bit 6

This bit is the complement of the Ring Indicator (RI)

input If bit 4 of the MCR is set to a 1 this bit is

equivalent to OUT1 in the MCR

Bit 7

This bit is the complement of the Data Carrier De-

tect (DCD) input If bit 4 of the MCR is set to a 1 this

bit is equivalent to IRQ ENABLE in the MCR

610 SCRATCHPAD REGISTER (SCR)

This 8-bit ReadWrite Register does not control the UART

in any way It is intended as a scratchpad register to be used

by the programmer to hold data temporarily

70 Serial Infrared Wireless

Communication Port

The PC87306 supports a serial InfraRed (IR) wireless com-

munication port An IR interface connects a UART’s serial in

and serial out signals via one or more transmitter LED and

receiver photo diode pairs

The IR port of the PC87306 is hooked to UART2 SOUT of

UART2 is also encoded by the PC87306 and routed to the

InfraRed Transmitter (IRTX) pin The InfraRed Receiver pin

(IRRX) is decoded by the PC87306 and routed to the SIN

signal of UART2

There are two UART2 interface modes

Normal (MODEM) mode The normal NS16550A UART

interface

IR mode InfraRed mode IrDA compliant

A system board can have a PC87306 configured with two

UARTs and one IR interface because these functions utilize

separate pins on the device The selection of UART2 inter-

face mode is a run-time selection that yields either two

PC87306 Datasheet(PDF) 68 Page - National Semiconductor (TI)

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