PC87306 datasheet(11/110 Pages) NSC

11 / 110 page

10 Pin Description (Continued)

TABLE 1-1 Pin Descriptions (Alphabetical)

(Continued)

Symbol

Function

DIR

FDC Direction

This output determines the direction of the floppy disk drive (FDD) head

movement (active e step in inactive e step out) during a seek operation During reads or writes

DIR is inactive

DR0 1

73 74

FDC Drive Select 0 1

These are the decoded Drive Select outputs that are controlled by the

Digital Output Register bits D0 D1 The Drive Select outputs are gated with DOR bits 4 – 7 These

are active low outputs They are encoded with information to control four FDDs when bit 4 of the

Function Enable Register (FER) is set (See MTR0 1 for more information)

DRATE0 1

82 81

FDC Data Rate 0 1

These outputs reflect the currently selected FDC data rate (bits 0 and 1 in

the Configuration Control Register (CCR) or the Data Rate Select Register (DSR) whichever was

written to last) These pins are totem-pole buffered outputs (6 mA sink 6 mA source)

DSKCHG

FDC Disk Change

This input indicates if the drive door has been opened The state of this pin is

available from the Digital Input register This pin can also be configured as the Read Gate

(RGATE) data separator diagnostic input via the Mode command (see Section 426)

DSR1 2

111 103

UARTs Data Set Ready

When low this signal indicates that the data set or MODEM is ready to

establish a communications link The DSR signal is a MODEM status input whose condition the

CPU can test by reading bit 5 (DSR) of the MODEM Status Register (MSR) for the appropriate

channel Bit 5 is the complement of the DSR signal Bit 1 (DDSR) of the MSR indicates whether

the DSR input has changed state since the previous reading of the MSR

Note

Whenever the DDSR bit of the MSR is set an interrupt is generated if MODEM Status interrupts are enabled

DSTRB

119

Data Strobe

This signal is used in EPP mode as a data strobe It is active low (See AFD and

Table 8-5 for further information)

DTR1 2

106 96

UARTs Data Terminal Ready

When low this output indicates to the MODEM or data set that

the UART is ready to establish a communications link The DTR signal can be set to an active low

by programming bit 0 (DTR) of the MODEM Control Register to a high level A Master Reset

operation sets this signal to its inactive (high) state Loop mode operation holds this signal to its

inactive state (See CFG0 1 for further information)

ERR

120

Error

A connected printer sets this input low when it has detected an error This pin has a

nominal 25 kX pull-up resistor attached to it

FDACK

FDC DMA Acknowledge

Active low input to acknowledge the FDC DMA request and enable the

RD and WR inputs during a DMA transfer When in PC-AT or Model 30 mode this signal is

enabled by bit D3 of the Digital Output Register (DOR) When in PS2 mode FDACK is always

enabled and bit D3 of the DOR is reserved FDACK should be held high during IO accesses

FDRQ

DMA Request

Active high output to signal the DMA controller that a FDC data transfer is

needed When in PC-AT or Model 30 mode this signal is enabled by bit D3 of the DOR When in

PS2 mode FDRQ is always enabled and bit D3 of the DOR is reserved

GPIO10–17

3-1

General Purpose IO10 – 17

General purpose IO pins of IO port 1

158 – 154

GPIO20–27

153 – 150

General Purpose IO20 – 27

General purpose IO pins of IO port 2

118 – 115

HCS0

Hard Drive Chip Select 0

This output is active in the PC-AT mode when 1) the hard drive

registers from 1F0 – 1F7h are selected and the primary address is used or 2) when the hard drive

registers from 170 – 177h are selected and the secondary address is used This output is inactive

if the IDE interface is disabled via the Configuration Register HCS0 is multiplexed with SELCS

strap input A 40 kX internal pull-up resistor is therefore used on this pin during reset (See

SELCS for further information)

HCS1

Hard Drive Chip Select 1

This output is active in the PC-AT mode when 1) the hard drive

registers from 3F6 – 7 are selected and the primary address is used or 2) the hard drive registers

from 376 – 377 are selected and the secondary address is used This output is also inactive if the

IDE interface is disabled via the Configuration Register

PC87306 Datasheet(PDF) 11 Page - National Semiconductor (TI)

PC87306 Datasheet(HTML) 11 Page - National Semiconductor (TI)

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL