PC87306 datasheet(71/110 Pages) NSC

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80 Parallel Port (Continued)

Bit 0

When in EPP mode this is the timeout status bit

When this bit is 0 no timeout

When this bit is 1 timeout occurred on EPP cycle

(minimum 10 ms)

It is cleared to 0 after STR is read ie consecutive

reads (after the first read) always return 0 It is also

cleared to 0 when EPP is enabled (bit 0 of PCR is

changed from 0 to 1)

When not in EPP mode this bit is 1

Bit 1

Reserved this bit is always 1

Bit 2

In the compatible mode (PTR7 bit is 0) or in ECP and

EPP modes this bit is always one

In the Extended Mode (PTR7 bit is 1) or in ECP and

EPP with bit 4 of PCR e 1 this bit is the IRQ

STATUS bit

In the Extended mode if CTR4 e 1 then this bit is

latched low when the ACK signal makes a transition

from low to high Reading this bit sets it to a one

Bit 3

This bit represents the current state of the printer

error signal (ERROR) The printer sets this bit low

when there is a printer error This bit follows the state

of the ERR pin

Bit 4

This bit represents the current state of the printer

select signal (SLCT) The printer sets this bit high

when it is selected This bit follows the state of the

SLCT pin

Bit 5

This bit represents the current state of the printer

paper end signal (PE) The printer sets this bit high

when it detects the end of the paper This bit follows

the state of the PE pin

Bit 6

This bit represents the current state of the printer

acknowledge signal (ACK) The printer pulses this

signal low after it has received a character and is

ready to receive another one This bit follows the

state of the ACK pin

Bit 7

This bit (BUSY) represents the current state of the

printer busy signal The printer sets this bit low when

it is busy and cannot accept another character This

bit is the inverse of the (BUSYWAIT) pin

84 CONTROL REGISTER (CTR)

TLC12379 – 41

This register provides all output signals to control the print-

er Except for bit 5 it is a read and write register

Bit 0

This bit (STB) directly controls the data strobe sig-

nal to the printer via the STB pin This bit is the

inverse of the STB pin

Bit 1

This bit (AFD) directly controls the automatic feed

XT signal to the printer via the AFD pin Setting this

bit high causes the printer to automatically feed

after each line is printed This bit is the inverse of

the AFD pin

Bit 2

This bit (INIT) directly controls the signal to initial-

ize the printer via the INIT pin Setting this bit to

low initializes the printer This bit follows the INIT

Note

This pin must be set to 1 before enabling the EPP or ECP

modes via bits 0 or 2 of the PCR register

Bit 3

This bit (SLIN) directly controls the select in signal

to the printer via the SLIN pin Setting this bit high

selects the printer It is the inverse of the SLIN pin

Bit 4

This bit controls the parallel port generated by the

ACK signal Its function changes slightly depend-

ing on the parallel port mode selected In ECP

mode this bit should be set to 0 In the following

description IRQx indicates either IRQ5 or IRQ7

(based upon PTR3)

Compatible mode

when bit 4 e 0 IRQx is floated

when bit 4 e 1 IRQx follows ACK transitions

Extended mode

when bit 4 e 0 IRQx is floated

when bit 4 e 1 IRQx becomes active on ACK trail-

ing edge

EPP mode

when bit 4 e 0 IRQx is floated

when bit 4 e 1 IRQx follows ACK transitions or

an EPP timeout occurs

Bit 5

This bit determines the parallel port direction when

bit 7 of PTR is 1 The default condition results in

the parallel port being in the output mode This is a

ReadWrite

bit in EPP mode and the software

should writea1toit In SPP mode it is a write only

bit a read from it will return 1 See Table 8-3 for

further details

Bits 6 7

Reserved These bits are always 1

Normally when the Control Register is read the bit values

are provided by the internal output data latch These bit

values can be superseded by the logic level of the STB

AFD INIT and SLIN pins if these pins are forced high or

low by an external voltage In order to force these pins high

or low the corresponding bits should be set to their inactive

state (eg AFD e STB e SLIN e 0 INIT e 1) See Table

8-4

TABLE 8-4 Parallel Port Reset States

Signal

Reset Control

State after Reset

SLIN

TRI-STATE

INIT

Zero

AFD

TRI-STATE

STB

TRI-STATE

IRQ5 7

TRI-STATE

85 ENHANCED PARALLEL PORT OPERATION

EPP mode provides for greater throughput and more com-

plexity than Compatible or Extended modes by supporting

faster transfer times and a mechanism that allows the host

to address peripheral device registers directly Faster trans-

fers are achieved by automatically generating the address

and data strobes EPP is compatible with both Compatible

and Extended mode parallel-port devices It consists of

eight (0 – 7) single-byte registers (See Table 8-5)

PC87306 Datasheet(PDF) 71 Page - National Semiconductor (TI)

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