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PC87306 Datasheet(PDF) 91 Page - National Semiconductor (TI) |
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PC87306 Datasheet(HTML) 91 Page - National Semiconductor (TI) |
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91 / 110 page  110 General Purpose Input and Output (GPIO) Ports The PC87306 supports two identical General Purpose IO (GPIO) ports See Figure 11-1 The PC87306 can wake up with both GPIO Ports either en- abled or disabled according to the CFG1 strap pin GPIO Port 1 is at offset 0 and GPIO Port 2 is at offset 1 from the 16-bit GPIO Port base address The GPIO port’s base ad- dress is software configurable GPBA is an 8-bit configura- tion register that holds address bit A2-9 (bit 0 holds A2) The other eight bits of the 16-bit GPIO port base address are 0 Upon reset GPBA is initialized to 00011110 thus dictating base address e 78h) The GPIO ports have open-drain outputs with internal pull- ups and TTL inputs The GPIO behave as follows 1 Writes are latched internally A latched 0 drives the pin low a latched 1 pulls the pin high via the internal pullup 2 Reads return the pins’ values A driven-low pin is always read as 0 A pulled-up pin is read as either 0 or 1 accord- ing to the pin voltage as dictated by the pullup or external active driver (TTL input buffers are used) Upon reset the write latches are initialized to FFh A GPIO port must not be enabled at the same address as another accessible PC87306 register Undefined results will occur if a GPIO is configured in this way TLC12379 – 65 FIGURE 11-1 General Purpose IO (GPIO) Ports 91 |
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