PC87306 datasheet(10/110 Pages) NSC

10 / 110 page

10 Pin Description

TABLE 1-1 Pin Descriptions (Alphabetical)

Symbol

Function

A0 – A15

61 – 59 56 – 46

Address

These address lines from the microprocessor determine which internal register is

accessed A0 – A10 are don’t cares during an DMA transfer A10 is used only during ECP

12–11

operations

ACK

127

Parallel Port Acknowledge

This input is pulsed low by a connected printer to indicate that it

has received data from the parallel port This pin has a nominal 25 kX pull-up resistor

attached to it (See DR1 and Table 7-5 for further information)

AFD

119

Parallel Port Automatic Feed

When this signal is low the printer should automatically line

feed after each line is printed This pin is in a TRI-STATE condition 10 ns aftera0is loaded

into the corresponding Control Register bit The system should pull this pin high using a 47

kX resistor (See DSTRB and Table 8-5 for further information)

AEN

Address Enable

This input disables function selection via A15 – A0 when it is high Access

during DMA transfer is NOT affected by this pin

ASTRB

123

Address Strobe

This signal is used in Enhanced Parallel Port (EPP) mode as an address

strobe It is active low (See SLIN and Table 8-5 for further information)

BADDR01

109 108

Base Address

These CMOS inputs are sensed during reset to determine one of four base

addresses from which the Index and Data Registers are offset (see Table 2-2) An internal

pull-down resistor of 30 kX is present on this pin Use a 10 kX resistor to pull this pin to VDD

(See RTS1 SOUT1 and BOUT1 for further information)

BOUT12

108 98

BAUD Output

This multi-function pin provides the associated serial channel Baud Rate

generator output signal when test mode is selected in the Power and Test Configuration

Output (SOUT) function (See SOUT and BADDR1 for further information)

BUSY

126

Parallel Port Busy

This pin is set high by a connected printer when it cannot accept another

character It has a nominal 25 kX pull-down resistor attached to it (See WAIT and Table 8-5

for further information)

CFG0 1

84 106

Configuration on Power-Up

These CMOS inputs select 1 of 4 default configurations in

which the PC87306 powers-up (see Table 2-1) They are provided with CMOS input buffers

An internal pull-down resistor of 30 kX is present on each pin Use a 10 kX resistor to pull

these pins to VDD

CS0 1

6 23

Programmable Chip Select

CS0 1 are programmable chip select andor latch enable and

or output enable signals that can be used for a game port IO port expander or other add-on

peripheral The decoded address and the assertion conditions are configured via the

PC87306 configuration registers 0Ah – 0Dh and 10h – 11h

CTS12

107 97

Clear to Send

When low this indicates that the MODEM or data set is ready to exchange

data The CTS signal is a MODEM status input whose condition the CPU can test by reading

bit 4 (CTS) of the MODEM Status Register (MSR) for the appropriate serial channel Bit 4 is

the complement of the CTS signal Bit 0 (DCTS) of the MSR indicates whether the CTS input

has changed state since the previous reading of the MSR CTS has no effect on the

transmitter

Note

Whenever the DCTS bit of the MSR is set an interrupt is generated if MODEM Status interrupts are enabled

D7 – 0

33 – 39 42

Data

Bi-directional data lines to the microprocessor D0 is the LSB and D7 is the MSB

These signals all have 24 mA (sink) buffered outputs

DCD12

112 104

UARTs Data Carrier Detect

When low this signal indicates that the MODEM or data set

has detected the data carrier The DCD signal is a MODEM status input whose condition the

CPU can test by reading bit 7 (DCD) of the MODEM Status Register (MSR) for the

appropriate serial channel Bit 7 is the complement of the DCD signal Bit 3 (DDCD) of the

MSR indicates whether the DCD input has changed state since the previous reading of the

MSR

Note

Whenever the DDCD bit of the MSR is set an interrupt is generated if MODEM Status interrupts are enabled

DENSEL

FDC Density Select

Indicates that a high FDC density data rate (500 kbps or 1 Mbps) or a

low density data rate (250 kbps or 300 kbps) is selected DENSEL’s polarity is controlled by

bit 6 of the ASC register

PC87306 Datasheet(PDF) 10 Page - National Semiconductor (TI)

PC87306 Datasheet(HTML) 10 Page - National Semiconductor (TI)

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL