PC87306 datasheet(23/110 Pages) NSC

23 / 110 page

20 Configuration Registers (Continued)

When this bit is 1 Version 19 is supported (IEEE

1284) and STB AFD INIT and SLIN are push-pull

outputs This bit has the same affect on the output

buffers in ECP modes 0 and 2

Bit 2

ECP enabIe bit When this bit is 0 the ECP is dis-

abled and in power-down mode The ECP registers

are not accessible (access ignored) and the ECP

interrupt and DMA are inactive When this bit is 1

the ECP is enabled The software should change

this bit to 1 only when bits 0 1 and 2 of the exist-

ing CTR are 1 0 and 0 respectively

Bit 3

ECP clock freeze control bit

In power-down

modes 2 and 3 When this bit is 0 the clock provid-

ed to the ECP is stopped and

When this bit is 1 the clock provided to the ECP is

not stopped

Bit 4

Reserved This bit must be set to 0

Bit 5

Parallel port interrupt (IRQ5 or IRQ7) polarity con-

trol bit When this bit is 0 the interrupt polarity is

level high or negative pulse When this bit is 1 the

interrupt polarity is inverted

Bit 6

Parallel port interrupt (IRQ5 or IRQ7) open drain

control bit When this bit is 0 the configured inter-

rupt line (IRQ5 or IRQ7) has a totem-pole output

When this bit is 1 the configured interrupt line has

an open drain output (drive low no drive high no

internal pullup)

Bit 7

RTC RAM write mask bit When this bit is 0 the

RTC RAM is writeable When this bit is 1 the RTC

RAM is not writeable and writes are ignored

256 KBC and RTC Control Register

(KRR Index e 05h)

This register enables and disables the keyboard controller

(KBC) and the Real-Time Clock (RTC) It selects the clock

source and operating mode of the KBC selects different

banks of CMOS RAM in the RTC and selects the RTC test

mode When MR is high KRR is initialized to 0X00XX01

Bits 2 and 3 are initialized according to CFG0 See Table

2-1 for initialization values upon reset

Bit 0

KBC Enable bit When this bit is zero the KBC

clock is frozen and the state of its dedicated pins

cannot be altered When this bit is one the KBC is

functional See Bit 2

Bit 1

KBC Speed control bit Controls the KBC speed

when X1 clock source is selected (KRR7 is 0) This

bit is ignored when SYSCLK clock source is se-

lected (KRR7 is 1)

When this bit is 0 the KBC clock is the X1 frequen-

cy divided by three (typically 8 MHz) When this bit

is 1 the KBC clock is the X1 frequency divided by

two (typically 12 MHz)

Bit 2

Reserved This bit must be set to 1 otherwise the

KBC will not be functional

Bit 3

RTC Enable bit When this bit is 0 the RTC is dis-

abled and IRQ8 is in TRI-STATE When this bit is 1

the RTC is enabled

Bit 4

Reserved

Bit 5

RAMSREL RTC CMOS RAM bank select When

this bit is 1 it selects the upper 128 bytes of CMOS

RAM When this bit is 0 it selects the lower

128 bytes of CMOS RAM

Bit 6

Reserved

Bit 7

KBC clock source select bit When this bit is 0 the

KBC uses the X1 clock source When this bit is 1

the KBC uses the SYSCLK clock source This bit

enables the KBC to operate in power-down mode

even when the X1 clock is frozen It may be modi-

fied only when the KBC is disabled via bit 0 of

KRR See Table 2-1

257 Power Management Control Register

(PMC Index e 06h)

This register controls the TRI-STATE and input pins The

PMC register is accessed through Index 06h The PMC Reg-

ister is cleared to X00XX000 on reset

Bit 0

IDE TRI-STATE Control bit

0 When this bit is 0 it does not affect the IDE

pins

1 IDE7 and HCS01 are in TRI-STATE IDEHI and

IDELO are inactive when either the IDE is dis-

abled or the chip is in power-down mode

Bit 1

FDC TRI-STATE Control bit

0 When this bit is 0 it does not affect the FDC

pins

1 The

FDC

outputs

except

IRQ6

are

TRI-STATE when either the FDC is disabled or

the chip is in power down mode

Bit 2

UART TRI-STATE Control bit

0 When this bit is 0 it does not affect the UART’s

pins

1 The outputs of any UART except IRQ4 and

IRQ3 are in TRI-STATE when that UART is dis-

abled or the chip is in power-down

Bits 3 4

Reserved

Bit 5

Selective Lock bit Unlike bit 6 of PTR which locks

all configuration bits this bit only enables locking

of the following

Bit 5 of PMC bit 4 of FER bits 0 – 7 of FAR bits 2

3 of PTR bit 1 of FCR and bit 5 of KRR Once this

bit has been set by software it can only be cleared

by a hardware reset It should be used instead of

bit 6 of PTR if a configration bit should be dynami-

cally modified by software (eg PMC bits)

0 No lock except via bit 6 of PTR

1 Any write to the above configuration bits is ig-

nored (until a hardware reset which clears this

bit)

Bit 6

Parallel Port TRI-STATE Control bit

0 When this bit is 0 it does not affect the parallel

port pins

1 The parallel port outputs except the configured

IRQ line (IRQ5 or IRQ7) are in TRI-STATE

when either the parallel port is disabled or the

chip is in power-down mode

Bit 7

Reserved

258 Tape UARTs and Parallel Port Configuration

The TUP Register is cleared to XXXXX0XX on reset

Bit 1

Reserved

PC87306 Datasheet(PDF) 23 Page - National Semiconductor (TI)

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