PC87306 datasheet(34/110 Pages) NSC

34 / 110 page

30 FDC Register Description (Continued)

Missing Address Mark in Data Field

Controller

cannot find the Data Field AM during a Read Scan

or Verify command Bit 0 of ST1 is also set

324 Status Register 3 (ST3)

DESC

TK0

HDS

DS1

DS0

RESET

101

COND

Not Used

Always 0

Write Protect

Indicates active high status of the WP

Not Used

Always 1

Track 0

Indicates active high status of the TRK0 pin

Not Used Always 1

Head Select

Indicates the active high status of the

HD bit in the Command Phase

D1 0 Drive Select 10

These two binary encoded bits indi-

cate the DS1 – DS0 bits in the Command Phase

40 FDC Command Set Description

This section presents the FDC command setfull descrip-

tion in Section 41 and a working summary in Section 42

Each command contains a unique first command byte the

opcode byte which tells the controller how many (0 or

more) command bytes to expect The information for each

command is displayed using the structure shown in

Figure

4-1

If an invalid command byte is issued to the controller it

immediately enters the Result Phase and the status is 80h

signifying an Invalid Command

IO Operation

Opcode

Command Byte 1

Command Byte 2

Command Byte n

FIGURE 4-1 FDC Command Structure

41 COMMAND DESCRIPTIONS

411 Configure Command

The Configure Command controls some operation modes of

the controller It should be issued during the initialization of

the FDC after power-up These bits are set to their default

values after a hardware reset The value of each bit after a

software reset is explained The default value of each bit is

denoted by a ‘‘bullet’’ to the left of each item

Command Phase

0011

0000

EIS

FIFO

POLL

THRESH

PRETRK

Execution Phase

Internal registers written

Result Phase

None

EIS

Enable Implied Seeks Default after a software reset

0 e Implied seeks disabled through Configure com-

mand Implied seeks can still be enabled through

the Mode command when EIS e 0

1 e

Implied seeks enabled for a read write scan or

verify operation A seek and sense interrupt oper-

ation is performed prior to the execution of the

read write scan or verify operation The IPS bit

does not need to be set

FIFO

Enable FIFO for Execution Phase data transfers De-

fault after a software reset if the LOCK bit is 0 If the

LOCK bit is 1 then the FIFO bit retains its previous

value after a software reset

0 e

FIFO enabled for both reads and writes

1 e FIFO disabled

POLL

Disable for Drive Polling Mode Default after a soft-

ware reset

0 e Enable drive polling mode An interrupt is gen-

erated after a reset

1 e

Disable drive polling mode If the Configure

command is issued within 500 ms of a hard-

ware or software reset then an interrupt is not

generated In addition the use of the four

Sense Interrupt commands to clear the ‘‘Ready

Changed State’’ of the four logical drives is not

required

THRESH

The FIFO threshold in the Execution Phase of

read and write data transfers Programmable

from 00h to 0Fh Defaults to 00h after a software

reset if the LOCK bit is 0 If the LOCK bit is 1

THRESH retains its value

A high value of

THRESH is suited for slow response systems

and a low value of THRESH is better for fast

response systems

PRETRK

Starting track number for write precompensation

Programmable from track 0 (‘‘00’’) to track 255

(‘‘FF’’) Defaults to track 0 (‘‘00’’) after a soft-

ware reset if the LOCK bit is 0 If the LOCK bit is

1 then PRETRK retains its value

412 Dumpreg Command

The Dumpreg command is designed to support system run-

time diagnostics application software development and de-

bug This command has a one-byte command phase and a

10-byte result phase The Result Phase returns the values

of parameters set in other commands That is the PTR

(Present Track Register) contains the least significant byte

of the track the microcode has stored for each drive The

Step Rate Time Motor Off and Motor On Times and the

DMA bit are all set in the Specify command

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