PC87306 datasheet(76/110 Pages) NSC

76 / 110 page

80 Parallel Port (Continued)

862 Software Operation

Software operation is detailed in the document

Extended

Capabilities Port Protocol and ISA Interface Standard To

highlight the ECP usage some software operations are de-

tailed below

1 The software should enable ECP (bit 2 of PCR is 1) after

bits 0 – 4 of the Parallel Port Control Register (CTR) are

00100

2 When ECP is enabled and the software wishes to switch

modes it should switch only through modes 000 or 001

3 When ECP is enabled the software should change direc-

tion only in mode 001

4 The software should switch from mode 010 or 011 to

mode 000 or 001 only when the FIFO is empty

5 The software should switch to mode 011 when bits 0 and

1 of DCR are 0

6 The software should switch to mode 010 when bit 0 of

DCR is 0

7 The software should disable ECP (bit 2 of PCR is 0) only

when in mode 000 or 001

Software may switch from mode 011 backward direction to

modes 000 or 001 when there is an on-going ECP read

cycle In this case the read cycle is aborted by deasserting

AFD The FIFO is reset (empty) and a potential byte expan-

sion (RLE) is automatically terminated since the new mode

is 000 or 001

The ZWS signal is asserted by the ECP when ECP is en-

abled and an ECP register is accessed by host PIO instruc-

tions thus using a host zero wait cycle

The ECP uses the X1OSC clock This clock can be frozen

(a power-down mode) When this power-down mode oc-

curs the DMA is disabled all interrupts (except ACK) are

masked and the FIFO registers are not accessible (access

is ignored) The other ECP registers are always accessible

when the ECP is enabled During this period the FIFO status

and contents are not lost although the host reads bit 2 of

ECR as 0 bit 1 of ECR as 1 and bit 0 of ECR as 1 regard-

less of the actual values of these bits When the clock starts

toggling again these bits resume their original functions (val-

ues)

When the clock is frozen an on-going ECP cycle may be

corrupted but next ECP cycle will not start This is true even

if in forward direction the FIFO is not empty and in back-

ward direction the FIFO is not full If the ECP clock starts or

stops toggling during a host cycle that accesses the FIFO

the cycle may yield wrong data

Note 1

The ECP outputs are inactive when the ECP is disabled

Note 2

Only the FIFODMARLE are not functional when the clock is fro-

zen All other registers are accessible and functional The FIFO

DMARLE are affected by ECR modifications ie they are reset

even when exits from modes 010011 are carried out while the

clock is frozen

87 REGISTER DEFINITIONS

DATAR

Same as DTR register except that read always

returns the values of the PD0 – PD7 pins (not the register

latched data)

AFIFO

ECP Address FIFO Register Write Only In the for-

ward direction (bit 5 of DCR is 0) a byte written into this

Reading this register has no effect and the data read is

undefined Writes to this register during backward direction

(bit 5 of DCR is 1) have no effect and the data is ignored

DSR

Read only Same as the current STR register except

for bit 2 which is reserved

Writes to this register have no effect and the data is ignored

Note

The FDC has a register of the same name (DSR)

DCR

Same as the SPP CTR register with the following

exceptions

1 When bit 5 of the DCR is 0 the ECP is in forward

direction and when bit 5 is high (1) the ECP is in

backward direction

2 The ECP drives the PD0 – PD7 pins in the forward

direction but does not drive them in the backward

direction

3 The direction bit bit 5 is readable and writable

4 When the control bit is read the bit values are

provided by the internal data latch These bit val-

ues are not superseded by the logic level of the

STB AFD INIT and SLIN pins

5 Bit 4 of the DCR enables the ACK deassertion

interrupt event (1 e enable 0 e mask) If a level

interrupt is configured (bit 4 of PCR is 1) clearing

this bit clears the ACK pending interrupt request

This bit does not float the IRQ pin

In mode 011 when bit 1 of DRC is 0 AFD is controlled by

ECP hardware When bit 1 of DCR is 1 AFD is driven low

In mode 011 or 010 when bit 0 of DCR is 0 STB is con-

trolled by the ECP hardware When bit 0 of DCR is 1 STB is

driven low

CFIFO

Parallel Port FIFO Register Write only

A byte written or DMAed to this register is pushed into the

FIFO and tagged as data

Reading this register has no effect and the data read is

undefined

DFIFO

ECP Data FIFO Register

In the forward direction (bit 5 of DCR is 0) a byte written or

DMAed to this register is pushed into the FIFO and tagged

as data

Reading this register has no effect and the data read is

undefined

In the backward direction (bit 5 of DCR is 1) the ECP auto-

matically issues ECP read cycles to fill the FIFO Reading

this register pops a byte from the FIFO

Writing this register has no effect and the data written is

ignored

TFIFO

Test FlFO Register

A byte written into this register is pushed into the FIFO A

byte read from this register is popped from the FIFO The

ECP does not issue a ECP cycle to transfer the data to or

from the peripheral device

The TFIFO is readable and writable in both directions In the

forward direction (bit 5 of DCR is 0) PD0 – PD7 are driven

but the data is undefined

PC87306 Datasheet(PDF) 76 Page - National Semiconductor (TI)

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