PC87306 datasheet(5/110 Pages) NSC

5 / 110 page

List of Figures

FIGURE 1-1

Pins Which Utilize the Strap Function during Reset

FIGURE 1-2

Multi-Function Pins

FIGURE 2-1

PC87306 Configuration Registers

FIGURE 2-2

PC87306 Four Floppy Drive Circuit

FIGURE 3-1

FDC Functional Block Diagram

FIGURE 4-1

FDC Command Structure

FIGURE 4-2

IBM Perpendicular and ISO Formats Supported by the Format Command

FIGURE 5-1

FDC Data Separator Block Diagram

FIGURE 5-2

PC87306 Dynamic Window Margin Performance

FIGURE 5-3

Read Data AlgorithmState Diagram

FIGURE 5-4

Perpendicular Recording Drive RW Head and Pre-Erase Head

FIGURE 6-1

PC87306 Composite Serial Data

FIGURE 6-2

Receiver FIFO Trigger Level

FIGURE 7-1

UART2 Serial and IR Interface Block Diagram

FIGURE 8-1

EPP 17 Address Write

FIGURE 8-2

EPP 17 Address Read

FIGURE 8-3

EPP Write with ZWS

FIGURE 8-4

EPP 19 Address Write

FIGURE 8-5

EPP 19 Address Read

FIGURE 8-6

ECP Forward Write Cycle

FIGURE 8-7

ECP Backward Read Cycle

FIGURE 9-1

IDE Interface Signal Equations (Non-DMA)

FIGURE 10-1

Keyboard Controller Functional Block Diagram

FIGURE 10-2

Keyboard Controller to Host System Interface

FIGURE 10-3

Status Register

FIGURE 10-4

Fast IRQ Latching and Clearing

FIGURE 10-5

Keyboard Controller Data Memory Map

FIGURE 10-7

PSW Register Bits

FIGURE 10-6

Keyboard Controller Stack Organization

FIGURE 10-8

Active Pull-Up IO Port Structure

FIGURE 10-9

Using Port Pins as Inputs

FIGURE 10-10

Timing Generation and Timer Circuit

FIGURE 10-11

External Clock Connection

FIGURE 10-12

Instruction Cycle Timing

FIGURE 10-13

Oscillator Internal and External Circuitry

FIGURE 10-14

InterruptStatus Timing

FIGURE 10-15

Typical Battery Configuration

FIGURE 10-16

Typical Battery Current during Battery Backed Mode

FIGURE 11-1

General Purpose IO (GPIO) Ports

FIGURE 12-1

Clock Timing

FIGURE 12-2

Microprocessor Read Timing

FIGURE 12-3

Microprocessor Write Timing

FIGURE 12-4

Read after Write Operation to All Registers and RAM Timing

FIGURE 12-5

Baud Out Timing

FIGURE 12-6

Transmitter Timing

FIGURE 12-7

Receiver Timing

FIGURE 12-8

FIFO Mode Receiver Timing

FIGURE 12-9

Timeout Receiver Timing

FIGURE 12-10

MODEM Control Timing

FIGURE 12-11

FDC DMA Timing

FIGURE 12-12

ECP DMA Timing

FIGURE 12-13

Reset Timing

FIGURE 12-14

Write Data Timing

PC87306 Datasheet(PDF) 5 Page - National Semiconductor (TI)

PC87306 Datasheet(HTML) 5 Page - National Semiconductor (TI)

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