M0519 datasheet(42/69 Pages) ETC2

42 / 69 page

M0519

Nov. 02, 2016

Page 42 of 69

Rev 1.02

Enhanced PWM Generator (EPWM)

6.8

6.8.1

Overview

This device has two built-in PWM units with the same architecture whose function is specially

designed for driving motor control applications.

6.8.2

Features

Each unit supports the features below:



Three independent 16-bit PWM duty control units with maximum 6 port pins:



3 independent PWM output:

EPWM0_CH0, EPWM0_CH2 and EPWM0_CH4 for Unit 0

EPWM1_CH0, EPWM1_CH2 and EPWM1_CH4 for Unit 1



3 complementary PWM pairs, with each pin in a pair mutually complement to each

other and capable of programmable dead-time insertion:

(EPWMx_CH0, EPWMx_CH1), (PWMx_CH2, EPWMx_CH3) and (EPWMx_CH4,

EPWMx_CH5) where x=0~1.



3 synchronous PWM pairs, with each pin in a pair in-phase:

(EPWMx_CH0, EPWMx_CH1), (EPWMx_CH2, EPWMx_CH3) and (EPWMx_CH4,

EPWMx_CH5) where x=0~1



Group control bits:

EPWMx_CH2 and EPWMx_CH4 are synchronized with EPWMx_CH0



Supports Edge aligned mode and Center aligned mode



Programmable dead-time insertion between complementary paired PWMs



Each pin of EPWMx_CH0 to EPWMx_CH5 has independent polarity setting control



Mask output control for Electrically Commutated Motor operation



Tri-state output at reset and brake state



Hardware brake protection



Two Interrupt Sources:



Interrupt is synchronously requested at PWM frequency when up/down counter

comparison matched (edge and center aligned modes) or underflow (center aligned

mode).



Interrupt is requested when external brake pins asserted



PWM signals before polarity control stage are defined in the view of positive logic. The PWM

ports is active high or active low are controlled by polarity control register.



High Source/Sink current.



Supports trigger EADC

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