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AD9690 Datasheet(PDF) 64 Page - Analog Devices

Part # AD9690
Description  Analog-to-Digital Converter
PDF  79 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

AD9690 Datasheet(HTML) 64 Page - Analog Devices

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Data Sheet
AD9690
Rev. B | Page 63 of 78
Table 32. Physical Layer 10-bit Input (Register 0x573[5:4]='b01)
10-Bit Symbol
Number
Alternating
Checkerboard
1/0 Word
Toggle
Ramp
PN9
PN23
User Repeat
User Single
0
0x155
0x000
(X) % 210
0x125
0x3FD
UP1[15:6]
UP1[15:6]
1
0x2AA
0x3FF
(X + 1) % 210
0x2FC
0x1C0
UP2[15:6]
UP2[15:6]
2
0x155
0x000
(X + 2) % 210
0x26A
0x00A
UP3[15:6]
UP3[15:6]
3
0x2AA
0x3FF
(X + 3) % 210
0x198
0x1B8
UP4[15:6]
UP4[15:6]
4
0x155
0x000
(X + 4) % 210
0x031
0x028
UP1[15:6]
0x000
5
0x2AA
0x3FF
(X + 5) % 210
0x251
0x3D7
UP2[15:6]
0x000
6
0x155
0x000
(X + 6) % 210
0x297
0x0A6
UP3[15:6]
0x000
7
0x2AA
0x3FF
(X + 7) % 210
0x3D1
0x326
UP4[15:6]
0x000
8
0x155
0x000
(X + 8) % 210
0x18E
0x10F
UP1[15:6]
0x000
9
0x2AA
0x3FF
(X + 9) % 210
0x2CB
0x3FD
UP2[15:6]
0x000
10
0x155
0x000
(X + 10) % 210
0x0F1
0x31E
UP3[15:6]
0x000
11
0x2AA
0x3FF
(X + 11) % 210
0x3DD
0x008
UP4[15:6]
0x000
Table 33. Scrambler 8-bit Input (Register 0x573[5:4]='b10)
8-Bit Octet
Number
Alternating
Checkerboard
1/0 Word
Toggle
Ramp
PN9
PN23
User Repeat
User Single
0
0x55
0x00
(X) % 28
0x49
0xFF
UP1[15:9]
UP1[15:9]
1
0xAA
0xFF
(X + 1) % 28
0x6F
0x5C
UP2[15:9]
UP2[15:9]
2
0x55
0x00
(X + 2) % 28
0xC9
0x00
UP3[15:9]
UP3[15:9]
3
0xAA
0xFF
(X + 3) % 28
0xA9
0x29
UP4[15:9]
UP4[15:9]
4
0x55
0x00
(X + 4) % 28
0x98
0xB8
UP1[15:9]
0x00
5
0xAA
0xFF
(X + 5) % 28
0x0C
0x0A
UP2[15:9]
0x00
6
0x55
0x00
(X + 6) % 28
0x65
0x3D
UP3[15:9]
0x00
7
0xAA
0xFF
(X + 7) % 28
0x1A
0x72
UP4[15:9]
0x00
8
0x55
0x00
(X + 8) % 28
0x5F
0x9B
UP1[15:9]
0x00
9
0xAA
0xFF
(X + 9) % 28
0xD1
0x26
UP2[15:9]
0x00
10
0x55
0x00
(X + 10) % 28
0x63
0x43
UP3[15:9]
0x00
11
0xAA
0xFF
(X + 11) % 28
0xAC
0xFF
UP4[15:9]
0x00
Data Link Layer Test Modes
The data link layer test modes are implemented in the AD9690
as defined by section 5.3.3.8.2 in the JEDEC JESD204B
Specification. These tests are shown in Register 0x574 Bits[2:0].
Test patterns inserted at this point are useful for verifying the
functionality of the data link layer. When the data link layer
test modes are enabled, disable SYNCINB± by writing 0xC0
to Register 0x572.



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