AD9690 datasheet(78/79 Pages) AD

78 / 79 page

Data Sheet

AD9690

Rev. B | Page 77 of 78

APPLICATIONS INFORMATION

POWER SUPPLY RECOMMENDATIONS

The AD9690 must be powered by the following seven supplies:

AVDD1 = 1.25 V, AVDD2 = 2.5 V, AVDD3 = 3.3 V, AVDD1_SR =

1.25 V, DVDD = 1.25 V, DRVDD = 1.25 V, and SPIVDD = 1.80 V.

For applications requiring an optimal high power efficiency and

low noise performance, it is recommended that the ADP2164

and ADP2370 switching regulators be used to convert the 3.3 V,

5.0 V, or 12 V input rails to an intermediate rail (1.8 V and 3.8 V).

These intermediate rails are then postregulated by very low

noise, low dropout (LDO) regulators (ADP1741, ADM7172,

and ADP125). Figure 114 shows the recommended power

supply scheme for AD9690.

AVDD1

1.25V

AVDD1_SR

1.25V

DVDD

1.25V

SPIVDD

(1.8V OR 3.3V)

3.6V

3.3V

DRVDD

1.25V

1.8V

ADP1741

ADP125

AVDD3

3.3V

ADM7172

ADP1741

AVDD2

2.5V

ADP1741

Figure 114. High Efficiency, Low Noise Power Solution for the AD9690

It is not necessary to split all of these power domains in all cases.

The recommended solution shown in Figure 114 provides the

lowest noise, highest efficiency power delivery system for the

AD9690. If only one 1.25 V supply is available, route to AVDD1

first and then tap it off and isolate it with a ferrite bead or a filter

choke, preceded by decoupling capacitors for AVDD1_SR, DVDD,

and DRVDD, in that order. This is shown as the optional path

in Figure 114. The user can employ several different decoupling

capacitors to cover both high and low frequencies. These capacitors

must be located close to the point of entry at the PCB level and

close to the devices, with minimal trace lengths.

EXPOSED PAD THERMAL HEAT SLUG

RECOMMENDATIONS

The exposed pad on the underside of the ADC must be connected

to AGND to achieve the best electrical and thermal performance

of the AD9690. Connect an exposed continuous copper plane

on the PCB to the AD9690 exposed pad, Pin 0.

The copper plane must have several vias to achieve the lowest

possible resistive thermal path for heat dissipation to flow

through the bottom of the PCB. These vias must be solder filled

or plugged. The number of vias and the fill determine the

resulting θJA measured on the board, as shown in Table 7.

To maximize the coverage and adhesion between the ADC and

PCB, partition the continuous copper plane by overlaying a

silkscreen on the PCB into several uniform sections. This

provides several tie points between the ADC and PCB during

the reflow process, whereas using one continuous plane with no

partitions only guarantees one tie point. See Figure 115 for a

PCB layout example. For detailed information on packaging

and the PCB layout of chip scale packages, see the AN-772

Application Note, A Design and Manufacturing Guide for the

Lead Frame Chip Scale Package (LFCSP).

Figure 115. Recommended PCB Layout of Exposed Pad for the AD9690

AVDD1_SR (PIN 57) AND AGND (PIN 56 AND PIN 60)

AVDD1_SR (Pin 57) and AGND (Pin 56 and Pin 60) can be

used to provide a separate power supply node to the SYSREF±

circuits of AD9690. If running in Subclass 1, the AD9690 can

support periodic one-shot or gapped signals. To minimize the

coupling of this supply into the AVDD1 supply node, adequate

supply bypassing is needed.

AD9690 Datasheet(PDF) 78 Page - Analog Devices

AD9690 Datasheet(HTML) 78 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79

Datasheet Download

Link URL