AD9690 datasheet(74/79 Pages) AD

74 / 79 page

Data Sheet

AD9690

Rev. B | Page 73 of 78

Reg

Addr

(Hex)

Name

Bit 7

(MSB)

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0 (LSB)

Default

Notes

0x561

Output

mode

Sample

invert

0 = normal

1 = sample

invert

Data format select

00 = offset binary

01 = twos complement

0x01

0x562

Output

overrange

(OR) clear

Virtual

Convert-

er 3 OR

0 = OR bit

enabled

1 = OR bit

cleared

Virtual

Converter 2

0 = OR bit

enabled

1 = OR bit

cleared

Virtual

Converter 1

0 = OR bit

enabled

1 = OR bit

cleared

Virtual

Converter

0 OR

0 = OR bit

enabled

1 = OR bit

cleared

0x00

0x563

Output OR

status

Virtual

Convert-

er 3 OR

0 = no OR

1 = OR

occurred

Virtual

Converter 2

0 = no OR

1 = OR

occurred

Virtual

Converter 1

0 = no OR

1 = OR

occurred

Virtual

Converter

0 OR

0 = no OR

1 = OR

occurred

0x00

Read

only

0x56E

JESD204B

lane rate

control

0 = serial

lane rate

≥6.25 Gbps

and

≤12.5 Gbps

1 = serial

lane rate

must be ≥

3.125 Gbps

and

≤6.25 Gbps

0x10

0x56F

JESD204B

PLL lock

status

PLL lock

0 = not

locked

1 = locked

0x00

Read

only

0x570

JESD204B

quick config-

uration

JESD204B quick configuration

L = number of lanes = 2Register0x570,Bits[7:6]

M = number of converters = 2Register0x570,Bits[5:3]

F = number of octets/frame = 2 Register0x570,Bits[2:0]

0x80 for

AD9690-

1000;

0x40 for

AD9690-

500

Refer to

Table 26

and

Table 27

0x571

JESD204B

Link Mode

Control 1

Standby

mode

0 = all

converter

outputs 0

1 = CGS

(/K28.5/)

Tail bit

(t) PN

0 =

disable

1 =

enable

T = N΄ −

N − CS

Long

transport

layer test

0 =

disable

1 =

enable

Lane synch-

ronization

0 = disable

FACI uses

/K28.7/

1 = enable

FACI uses

/K28.3/ and

/K28.7/

ILAS sequence mode

00 = ILAS disabled

01 = ILAS enabled

11 = ILAS always on test

mode

FACI

0 =

enabled

1 =

disabled

Link

control

0 = active

1 = power

down

0x14

0x572

JESD204B

Link Mode

Control 2

SYNCINB± pin control

00 = normal

10 = ignore SYNCINB±

(force CGS)

11 = ignore SYNCINB±

(force ILAS/user data)

SYNCINB±

pin invert

0 = active

low

1 = active

high

SYNCINB±

pin type

0 =

differential

1 = CMOS

8-bit/10-bit

bypass

0 = normal

1 = bypass

8-/10-bit

bit invert

0 =

normal

1 = invert

the abcd

efghij

symbols

0x00

0x573

JESD204B

Link Mode

Control 3

CHKSUM mode

00 = sum of all 8-bit link

config registers

01 = sum of individual

link config fields

10 = checksum set to

zero

Test injection point

00 = N΄ sample input

01 = 10-bit data at

8-bit/10-bit output

(for PHY testing)

10 = 8-bit data at

scrambler input

JESD204B test mode patterns

0000 = normal operation (test mode disabled)

0001 = alternating checker board

0010 = 1/0 word toggle

0011 = 31-bit PN sequence—X31 + X28 + 1

0100 = 23-bit PN sequence—X23+ X18 + 1

0101 = 15-bit PN sequence—X15 + X14 + 1

0110 = 9-bit PN sequence—X9 + X5 + 1

0111 = 7-bit PN sequence—X7 + X6 + 1

1000 = ramp output

1110 = continuous/repeat user test

1111 = single user test

0x00

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