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AD9690

Data Sheet

Rev. B | Page 32 of 78

SIGNAL MONITOR

The signal monitor block provides additional information about

the signal being digitized by the ADC. The signal monitor

computes the peak magnitude of the digitized signal. This

information can be used to drive an AGC loop to optimize the

range of the ADC in the presence of real-world signals.

The results of the signal monitor block can be obtained either by

reading back the internal values from the SPI port or by embedding

the signal monitoring information into the JESD204B interface as

special control bits. A 24-bit programmable period controls the

duration of the measurement. Figure 84 shows the simplified block

diagram of the signal monitor block.

FROM

MEMORY

MAP

DOWN

COUNTER

COUNT = 1?

MAGNITUDE

STORAGE

FROM

INPUT

SIGNAL

MONITOR

HOLDING

LOAD

CLEAR

COMPARE

A > B

LOAD

TO SPORT OVER

JESD204B AND

MEMORY MAP

SIGNAL MONITOR

PERIOD REGISTER

(SMPR)

0x271, 0x272, 0x273

Figure 84. Signal Monitor Block

The peak detector captures the largest signal within the

observation period. The detector only observes the magnitude

of the signal. The resolution of the peak detector is a 13-bit

value, and the observation period is 24 bits and represents

converter output samples. The peak magnitude can be derived

by using the following equation:

Peak Magnitude (dBFS) = 20log(Peak Detector Value/213)

The magnitude of the input port signal is monitored over a

programmable time period, which is determined by the signal

monitor period register (SMPR). The peak detector function is

enabled by setting Bit 1 of Register 0x270 in the signal monitor

control register. The 24-bit SMPR must be programmed before

activating this mode.

After enabling peak detection mode, the value in the SMPR is

loaded into a monitor period timer, which decrements at the

decimated clock rate.

The magnitude of the input signal is compared with the value in

the internal magnitude storage register (not accessible to the

user), and the greater of the two is updated as the current peak

level. The initial value of the magnitude storage register is set to

the current ADC input signal magnitude. This comparison

continues until the monitor period timer reaches a count of 1.

When the monitor period timer reaches a count of 1, the 13-bit

peak level value is transferred to the signal monitor holding

through the SPORT over the JESD204B interface. The monitor

period timer is reloaded with the value in the SMPR, and the

countdown is restarted. In addition, the magnitude of the first

input sample is updated in the magnitude storage register, and

the comparison and update procedure, as explained previously,

continues.

SPORT OVER JESD204B

The signal monitor data can also be serialized and sent over the

JESD204B interface as control bits. These control bits must be

deserialized from the samples to reconstruct the statistical data.

The signal control monitor function is enabled by setting Bits[1:0]

of Register 0x279 and Bit 1 of Register 0x27A. Figure 85 shows

two different example configurations for the signal monitor

control bit locations inside the JESD204B samples. A maximum

of three control bits can be inserted into the JESD204B samples;

however, only one control bit is required for the signal monitor.

Control bits are inserted from MSB to LSB. If only one control bit

is to be inserted (CS = 1), only the most significant control bit is

used (see Example Configuration 1 and Example Configuration 2

in Figure 85). To select the SPORT over JESD204B option,

program Register 0x559, Register 0x55A, and Register 0x58F.

See Table 36 for more information on setting these bits.

Figure 86 shows the 25-bit frame data that encapsulates the

peak detector value. The frame data is transmitted MSB first

with five 5-bit subframes. Each subframe contains a start bit

that can be used by a receiver to validate the deserialized data.

Figure 87 shows the SPORT over JESD204B signal monitor data

with a monitor period timer set to 80 samples.

AD9690 Datasheet(PDF) 33 Page - Analog Devices

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