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AD9690 Datasheet(PDF) 9 Page - Analog Devices

Part # AD9690
Description  Analog-to-Digital Converter
PDF  79 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

AD9690 Datasheet(HTML) 9 Page - Analog Devices

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AD9690
Data Sheet
Rev. B | Page 8 of 78
Parameter
Temperature
Min
Typ
Max
Unit
LOGIC OUTPUT (FD)
Logic Compliance
Full
CMOS
Logic 1 Voltage
Full
0.8
SPIVDD
V
Logic 0 Voltage
Full
0
0
V
Input Resistance
Full
30
kΩ
DIGITAL OUTPUTS (SERDOUTx±, x = 0 TO 3)
Logic Compliance
Full
CML
Differential Output Voltage
Full
360
770
mV p-p
Output Common-Mode Voltage (VCM)
AC Coupled
25°C
0
1.8
V
Short-Circuit Current (IDSHORT)
25°C
−100
+100
mA
Differential Return Loss (RLDIFF)1
25°C
8
dB
Common-Mode Return Loss (RLCM)1
25°C
6
dB
Differential Termination Impedance
Full
80
100
120
Ω
1
Differential and common-mode return loss is measured from 100 MHz to 0.75 MHz × baud rate.
SWITCHING SPECIFICATIONS
AVDD1 = 1.25 V, AVDD2 = 2.5 V, AVDD3 = 3.3 V, AVDD1_SR = 1.25 V, DVDD = 1.25 V, DRVDD = 1.25 V, SPIVDD = 1.8 V, specified
maximum sampling rate for each speed grade, AIN = −1.0 dBFS, default SPI settings, TA = 25°C, unless otherwise noted.
Table 4.
AD9690-500
AD9690-1000
Parameter
Temperature
Min
Typ
Max
Min
Typ
Max
Unit
CLOCK
Clock Rate (at CLK+/CLK− Pins)
Full
0.3
4
0.3
4
GHz
Maximum Sample Rate1
Full
500
1000
MSPS
Minimum Sample Rate2
Full
300
300
MSPS
Clock Pulse Width High
Full
1000
500
ps
Clock Pulse Width Low
Full
1000
500
ps
OUTPUT PARAMETERS
Unit Interval (UI)3
Full
80
200
80
100
ps
Rise Time (tR) (20% to 80% into 100 Ω Load)
25°C
24
32
24
32
ps
Fall Time (tF) (20% to 80% into 100 Ω Load)
25°C
24
32
24
32
ps
PLL Lock Time
25°C
2
2
ms
Data Rate (NRZ)4
25°C
3.125
5
12.5
3.125
10
12.5
Gbps
LATENCY5
Pipeline Latency
Full
55
55
Clock cycles
Fast Detect Latency
Full
28
28
Clock cycles
Wake-Up Time6
Standby
25°C
1
1
ms
Power-Down
25°C
4
4
ms
APERTURE
Aperture Delay (tA)
Full
530
530
ps
Aperture Uncertainty (Jitter, tj)
Full
55
55
fs rms
Out-of-range Recovery Time
Full
1
1
Clock Cycles
1
The maximum sample rate is the clock rate after the divider.
2
The minimum sample rate operates at 300 MSPS with L = 2 or L = 1.
3
Baud rate = 1/UI. A subset of this range can be supported.
4
Default L = 4. This number can be changed based on the sample rate and decimation ratio.
5
No DDCs used. L = 2, M = 1, F = 1.
6
Wake-up time is defined as the time required to return to normal operation from power-down mode.



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