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AD9690 Datasheet(PDF) 69 Page - Analog Devices |
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AD9690 Datasheet(HTML) 69 Page - Analog Devices |
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69 / 79 page  AD9690 Data Sheet Rev. B | Page 68 of 78 Reg Addr (Hex) Register Name Bit 7 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSB) Default Notes 0x10C Clock divider phase 0 0 0 0 Independently controls ADC clock divider phase offset 0000 = 0 input clock cycles delayed 0001 = ½ input clock cycles delayed 0010 = 1 input clock cycles delayed 0011 = 1½ input clock cycles delayed 0100 = 2 input clock cycles delayed 0101 = 2½ input clock cycles delayed … 1111 = 7½ input clock cycles delayed 0x00 0x10D Clock divider and SYSREF control Clock divider auto phase adjust 0 = disabled 1 = enabled 0 0 0 Clock divider negative skew window 00 = no negative skew 01 = 1 device clock of negative skew 10 = 2 device clocks of negative skew 11 = 3 device clocks of negative skew Clock divider positive skew window 00 = no positive skew 01 = 1 device clock of positive skew 10 = 2 device clocks of positive skew 11 = 3 device clocks of positive skew 0x00 Clock divider must be >1 0x117 Clock delay control 0 0 0 0 0 0 0 Clock fine delay adjust enable 0 = disabled 1 = enabled 0x00 Enabling the clock fine delay adjust causes a datapath reset 0x118 Clock fine delay Clock fine delay adjust[7:0], twos complement coded control to adjust the fine sample clock skew in ~1.7 ps steps ≤ −88 = −151.7 ps skew −87 = −150 ps skew … 0 = 0 ps skew … ≥ +87 = +150 ps skew 0x00 Used in con- junction with Reg. 0x0117 0x11C Clock status 0 0 0 0 0 0 0 0 = no input clock detected 1 = input clock detected Read only 0x120 SYSREF± Control 1 0 SYSREF± flag reset 0 = normal operat- ion 1 = flags held in reset 0 SYSREF± transition select 0 = low to high 1 = high to low CLK± edge select 0 = rising 1 = falling SYSREF± mode select 00 = disabled 01 = continuous 10 = N shot 0 0x00 0x121 SYSREF± Control 2 0 0 0 0 SYSREF N-shot ignore counter select 0000 = next SYSREF± only 0001 = ignore the first SYSREF± transitions 0010 = ignore the first two SYSREF± transitions … 1111 = ignore the first 16 SYSREF± transitions 0x00 Mode select (Reg 0x120, Bits [2:1]) must be N-shot 0x123 SYSREF± timestamp delay control SYSREF± timestamp delay, Bits[6:0] 0x00 = no delay 0x01 = 1 clock delay … 0x7F = 127 clocks delay 0x00 Ignored when Reg. 0x01FF = 0x00 0x128 SYSREF± Status 1 SYSREF± hold status, Register 0x128[7:4], refer to Table 28 SYSREF± setup status, Register 0x128[3:0], refer to Table 28 Read only |
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