AD9250 datasheet(36/45 Pages) AD

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AD9250

Data Sheet

Rev. E | Page 36 of 45

MEMORY MAP

READING THE MEMORY MAP REGISTER TABLE

Each row in the memory map register table has eight bit locations.

The memory map is roughly divided into three sections: the

chip configuration registers (Address 0x00 to Address 0x02);

the channel index and transfer registers (Address 0x05 and

Address 0xFF); and the ADC functions registers, including

setup, control, and test (Address 0x08 to Address 0xA8).

The memory map register table (see Table 18) documents the

default hexadecimal value for each hexadecimal address shown.

The column with the heading Bit 7 (MSB) is the start of the

default hexadecimal value given. For example, Address 0x14,

the output mode register, has a hexadecimal default value of

0x01. This means that Bit 0 = 1, and the remaining bits are 0s.

This setting is the default output format value, which is twos

complement. For more information on this function and others,

see the AN-877 Application Note, Interfacing to High Speed

ADCs via SPI. This document details the functions controlled

by Register 0x00 to Register 0x25. The remaining registers,

Memory Map Register Description section.

Open and Reserved Locations

All address and bit locations that are not included in Table 18

are not currently supported for this device. Unused bits of a valid

address location should be written with 0s. Writing to these

locations is required only when part of an address location is

open (for example, Address 0x18). If the entire address location

is open (for example, Address 0x13), do not write to this

address location.

Default Values

After the AD9250 is reset, critical registers are loaded with

default values. The default values for the registers are given

in the memory map register table, Table 18.

Logic Levels

An explanation of logic level terminology follows:

•

“Bit is set” is synonymous with “bit is set to Logic 1” or

“writing Logic 1 for the bit.”

•

“Clear a bit” is synonymous with “bit is set to Logic 0” or

“writing Logic 0 for the bit.”

Channel-Specific Registers

Some channel setup functions, such as dc offset adjust or ouput

data format, can be programmed to a different value for each

channel. In these cases, channel address locations are internally

duplicated or shadowed for each channel. These registers and bits

are designated as local in Table 18. Note that all other listed

registers are considered as global; write operations to these

registers affect the entire device upon completion of the write

operation.

Local registers and bits can be accessed by setting the appropriate

Channel A or Channel B bits in Register 0x05. If both bits are

set, the subsequent write affects the registers of both channels.

In a read cycle, set only Channel A or Channel B to read one of

the two registers. If both bits are set during an SPI read cycle,

the device returns the value for Channel A.

To write to a specific channel, the following three steps must

occur:

1. Select the desired channel(s) for SPI write operation via

2. Perform the specific write operation to desired local SPI

3. Transfer of the write operation contents to the target local

when the transfer bit is set. The internal update takes place

when the transfer bit is set and then the bit automatically

clears.

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