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AD9250 Datasheet(PDF) 29 Page - Analog Devices

Part # AD9250
Description  Dual Analog-to-Digital Converter
PDF  45 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

AD9250 Datasheet(HTML) 29 Page - Analog Devices

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Data Sheet
AD9250
Rev. E | Page 29 of 45
8B/10B
ENCODER/
CHARACTER
REPLACEMENT
SERIALIZER
t
..
.
~SYNC
SYSREF
VINA+
(MSB)
(LSB)
VINA–
SERDOUT±
A PATH
ADC
TEST PATTERN
16-BIT
JESD204B
TEST PATTERN
8-BIT
ADC
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
C0
C1
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
S0
S1
S2
S3
S4
S5
S6
S7
S8
S9
S10
S11
S12
S13
S14
S15
E0
E1
E2
E3
E4
E5
E6
E7
E10
E11
E12
E13
E14
E15
E16
E17
E8
E9
E0
E1
E2
E3
E4
E5
E6
E7
E8
E9
E18
E19
E19
OPTIONAL
SCRAMBLER
1 + x14 + x15
JESD204B
TEST PATTERN
10-BIT
Figure 55. AD9250 Digital Processing of JESD204B Lanes
Table 13. AD9250 JESD204B Typical Configurations
JESD204B
Configure
Setting
M (No. of Converters),
Register 0x71,
Bits[7:0]
L (No. of Lanes),
Register 0x6E,
Bit 0
F (Octets/Frame),
Register 0x6F,
Bits[7:0], Read Only
S (Samples/ADC/Frame),
Register 0x74, Bits[4:0],
Read Only
HD (High Density Mode),
Register 0x75, Bit 7,
Read Only
0x11
1
1
2
1
0
0x12
1
2
1
1
1
0x21
2
1
4
1
0
0x22 (Default)
2
2
2
1
0
DATA
FROM
ADC
FRAME
ASSEMBLER
(ADD TAIL BITS)
OPTIONAL
SCRAMBLER
1 + x14 + x15
8B/10B
ENCODER
TO
RECEIVER
Figure 56. AD9250 ADC Output Data Path



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