AD9250

Data Sheet

Rev. E | Page 30 of 45

Table 14. AD9250 JESD204B Configuration, Register 0x3A

Bit No.

Register Description

Functional Description

0

Enable internal

SYSREF buffer

This bit controls the on-chip buffer for the SYSREF singal. By default, this bit is 0, which disables the buffer. If the

AD9250 is configured for JESD204B Subclass 1 operation, SYSREF is required to align the JESD204B link and this

bit must be set to 1.

To avoid a false trigger as a result of transients caused when enabling the buffer (particularly for one-shot SYSREF

configuration), set this bit first and then in a consecutive SPI register write, configure all remaining bits in Register 0x3A

to the desired JESD204B link configuration, including keeping this bit at 1.

A setting of 0 (default) gates the SYSREF signal such that the internal logic is not affected by an external SYSREF.

Set this bit to 0 when in Subclass 0, that is, when SYSREF is not used.

If using Subclass 1 with one-shot SYSREF mode, enable the buffer while the SYSREF is established, but then

disable it during normal operation.

If using Subclass 1 with continuous SYSREF mode, the buffer must remain enabled for normal operation.

1

SYSREF± enable

This bit enables the circuitry that uses the SYSREF input signal and must be on to enable Subclass 1 operation.

Set this bit to 1 when using JESD204B Subclass 1 operation.

This bit is self clearing after a valid SYSREF occurs when SYSREF± mode (Register 0x3A, Bit 2) is set to 1

(configured for one-shot SYSREF operation).

Note that SYSREF is still used in some digital circuitry even if this bit is 0; to disable the SYSREF signal internally,

Register 0x3A Bit 0 must be set to 0.

2

SYSREF± mode

This bit is used in Subclass 1 operation to define one shot or continuous SYSREF mode. To configure continuous

(or gapped periodic) SYSREF, this bit is set to 0. For one-shot operation, this bit is set to 1. In one-shot mode, it is

recommended that the SYSREF buffer be disabled after SYSREF has occurred by setting Register 0x3A, Bit 0 to 0.

3

Realign on SYSREF;

forSubclass 1 only

When this bit is set to 1, the internal clock alignment for the JESD204B timing is forced when an active SYSREF

occurs. This is recommended only for one-shot mode and must only be done prior to initially establishing a link. This

resets the JESD204B link on active SYSREF.

For continuous SYSREF mode, this bit must be set to 0 during normal operation.

4

Realign on SYNCB;

for Subclass 1 only

When this bit is set to 1, the internal clock alignment for the JESD204B timing is forced when an active SYNC

occurs. An active SYNC requires the SYNCINB input to be logic low for at least four consecutive LMFCs.

Table 15. AD9250 JESD204B Frame Alignment Monitoring and Correction Replacement Characters

Scrambling

Lane Synchronization

Character to be Replaced

Last Octet in Multiframe

Replacement Character

Off

On

Last octet in frame repeated from previous frame

No

K28.7

Off

On

Last octet in frame repeated from previous frame

Yes

K28.3

Off

Off

Last octet in frame repeated from previous frame

Not applicable

K28.7

On

On

Last octet in frame equals D28.7

No

K28.7

On

On

Last octet in frame equals D28.3

Yes

K28.3

On

Off

Last octet in frame equals D28.7

Not applicable

K28.7

FRAME AND LANE ALIGNMENT MONITORING

AND CORRECTION

Frame alignment monitoring and correction is part of the JESD204B

specification. The 14-bit word requires two octets to transmit all

the data. The two octets (MSB and LSB), where F = 2, make up

a frame. During normal operating conditions, frame alignment

is monitored via alignment characters, which are inserted under

certain conditions at the end of a frame. Table 15 summarizes the

conditions for character insertion along with the expected characters

under the various operation modes. If lane synchronization is

enabled, the replacement character value depends on whether

the octet is at the end of a frame or at the end of a multiframe.

Based on the operating mode, the receiver can ensure that it is

still synchronized to the frame boundary by correctly receiving

the replacement characters.

DIGITAL OUTPUTS AND TIMING

The AD9250 has differential digital outputs that power up by default.

The driver current is derived on-chip and sets the output current at

each output equal to a nominal 4 mA. Each output presents a 100 Ω

dynamic internal termination to reduce unwanted reflections.

Place a 100 Ω differential termination resistor at each receiver input

to result in a nominal 300 mV peak-to-peak swing at the receiver

(see Figure 57). Alternatively, single-ended 50 Ω termination

can be used. When single-ended termination is used, the

termination voltage should be DRVDD/2; otherwise, ac coupling

capacitors can be used to terminate to any single-ended voltage.

100Ω

OR

100Ω

DIFFERENTIAL

TRACE PAIR

SERDOUTx+

DRVDD

SERDOUTx–

(SEE TABLE 3)

0.1µF

0.1µF

RECEIVER

Figure 57. AC-Coupled Digital Output Termination Example