AD9250 datasheet(27/45 Pages) AD

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Data Sheet

AD9250

Rev. E | Page 27 of 45

Configure Detailed Options

Configure the tail bits and control bits.

•

With N’ = 16 and N = 14, there are two bits available per

sample for transmitting additional information over the

JESD204B link. The options are tail bits or control bits. By

default, tail bits of 0b00 value are used.

•

Tail bits are dummy bits sent over the link to complete the

two octets and do not convey any information about the input

signal. Tail bits can be fixed zeros (default) or psuedo

random numbers (Register 0x5F, Bit 6).

•

One or two control bits can be used instead of the tail bits

through Register 0x72, Bits[7:6]. The tail bits can be set

using Register 0x14, Bits[7:5], and can be enabled using

Address 0x5F, Bit 6.

Set lane identification values.

•

JESD204B allows parameters to identify the device and

lane. These parameters are transmitted during the ILAS

phase, and they are accessible in the internal registers.

•

There are three identification values: device identification

(DID), bank identification (BID), and lane identification

(LID). DID and BID are device specific; therefore, they can

be used for link identification.

Set number of frames per multiframe, K

•

Per the JESD204B specification, a multiframe is defined as a

group of K successive frames, where K is between 1 and 32,

and it requires that the number of octets be between 17 and

1024. The K value is set to 32 by default in Register 0x70,

Bits[7:0]. Note that Register 0x70 represents a value of K − 1.

•

The K value can be changed; however, it must comply with

a few conditions. The AD9250 uses a fixed value for octets

per frame [F] based on the JESD204B quick configuration

setting. K must also be a multiple of 4 and conform to the

following equation.

32 ≥ K ≥ Ceil (17/F)

•

The JESD204B specification also calls for the number of

octets per multiframe (K × F) to be between 17 and 1024.

The F value is fixed through the quick configuration

setting to ensure this relationship is true.

Table 11. JESD204B Configurable Identification Values

DID Value

Value Range

LID (Lane 0)

0x66, [4:0]

0…31

LID (Lane 1)

0x67, [4:0]

0…31

DID

0x64, [7:0]

0…255

BID

0x65, [3:0]

0…15

Scramble, SCR.

•

Scrambling can be enabled or disabled by setting Register 0x6E,

Bit 7. By default, scrambling is enabled. Per the JESD204B

protocol, scrambling is only functional after the lane

synchronization has completed.

Select lane synchronization options.

Most of the synchronization features of the JESD204B interface

are enabled by default for typical applications. In some cases,

these features can be disabled or modified as follows:

•

ILAS enabling is controlled in Register 0x5F, Bits[3:2] and

by default is enabled. Optionally, to support some unique

instances of the interfaces (such as NMCDA-SL), the

JESD204B interface can be programmed to either disable

the ILAS sequence or continually repeat the ILAS sequence.

The AD9250 has fixed values of some of the JESD204B interface

parameters, and they are as follows:

•

[N] = 14: number of bits per converter is 14, in Register 0x72,

Bits[4:0]; Register 0x72 represents a value of N − 1.

•

[N’] = 16: number of bits per sample is 16, in Register 0x73,

Bits[4:0]; Register 0x73 represents a value of N’ − 1.

•

[CF] = 0: number of control words/ frame clock

cycle/converter is 0, in Register 0x75, Bits[4:0].

Verify read only values: lanes per link (L), octets per frame (F),

number of converters (M), and samples per converter per frame

(S). The AD9250 calculates values for some JESD204B parameters

based on other settings, particularly the quick configuration

•

[L] = lanes per link can be 1 or 2, read the values from

•

[F] = octets per frame can be 1, 2, or 4, read the value from

•

[HD] = high density mode can be 0 or 1, read the value

from Register 0x75, Bit 7

•

[M] = number of converters per link can be 1 or 2, read the

value from Register 0x71, Bits[7:0]

•

[S] = samples per converter per frame can be 1 or 2, read

the value from Register 0x74, Bits[4:0]

Check FCHK, Checksum of JESD204B Interface Parameters

The JESD204B parameters can be verified through the checksum

value [FCHK] of the JESD204B interface parameters. Each lane has

a FCHK value associated with it. The FCHK value is transmitted

during the ILAS second multiframe and can be read from the

internal registers.

The checksum value is the modulo 256 sum of the parameters

listed in the No. column of Table 12. The checksum is calculated

by adding the parameter fields before they are packed into the

octets shown in Table 12.

The FCHK for the lane configuration for data coming out of

Lane 0 can be read from Register 0x78. Similarly, the FCHK for

the lane configuration for data coming out of Lane 1 can be read

from Register 0x79.

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