AD9250 datasheet(33/45 Pages) AD

33 / 45 page

Data Sheet

AD9250

Rev. E | Page 33 of 45

DC CORRECTION

Because the dc offset of the ADC may be significantly larger than

the signal being measured, a dc correction circuit is included to

null the dc offset before measuring the power. The dc correction

circuit can also be switched into the main signal path; however,

this may not be appropriate if the ADC is digitizing a time-varying

signal with significant dc content, such as GSM.

DC CORRECTION BANDWIDTH

The dc correction circuit is a high-pass filter with a program-

mable bandwidth (ranging between 0.29 Hz and 2.387 kHz

at 245.76 MSPS). The bandwidth is controlled by writing to

the 4-bit dc correction bandwidth select register, located at

to compute the bandwidth value for the dc correction circuit:

DC_Corr_BW = 2−k−14 × fCLK/(2 × π)

where:

k is the 4-bit value programmed in Bits[5:2] of Register 0x40

(values between 0 and 13 are valid for k).

fCLK is the AD9250 ADC sample rate in hertz.

DC CORRECTION READBACK

The current dc correction value can be read back in Register 0x41

and Register 0x42 for each channel. The dc correction value is a

16-bit value that can span the entire input range of the ADC.

DC CORRECTION FREEZE

Setting Bit 6 of Register 0x40 freezes the dc correction at its

current state and continues to use the last updated value as the

dc correction value. Clearing this bit restarts dc correction and

adds the currently calculated value to the data.

DC CORRECTION (DCC) ENABLE BITS

Setting Bit 1 of Register 0x40 enables dc correction for use in

the output data signal path.

AD9250 Datasheet(PDF) 33 Page - Analog Devices