AD9250

Data Sheet

Rev. E | Page 44 of 45

Step

Address

Write

Value

Comments

11

Optional: JESD204B Subclass 1 synchronization setup.

0x3A

0x01

Enable the SYSREF buffer first to avoid false triggering (especially one-shot operation) before setting the

remaining bits in Register 0x3A.

0xFF

0x01

Transfer command for local Register

0x3A

0x0F or

0x03

Configure the method of SYSREF operation. For one-shot operation, set to 0x0F. For continuous or gapped

periodic SYSREF operation, set to 0x03.

0xFF

0x01

Transfer command for local Register

12

Begin JESD204B link establishment.

0x0A

Optional: read back Register 0x0A with 0x81 indicating that the JESD204B PLL is locked.

0x5F

0x14

Enable the JESD204B PHY. This begins the CGS phase for establishing a link.

0xF3

0xFF

Force an internal FIFO alignment.

Wait at least six LMFC cycles.

Note that the JESD204B link must be established at this time before continuing.

13

Optional: When operating in SubClass 1 mode, apply external SYSREF signal for LMFC alignment.

Wait at least six LMFC cycles for LMFC alignment between JESD204B Tx and Rx to occur.

0x3A

0x04

Conditional: disable the internal SYSREF buffer if configured for one-shot operation.

0xFF

0x01

Transfer command for local Register

14

Internal FIFO clock adjustment.

0xEE

0x81

0xEF

0x81

0xEE

0x82

0xEF

0x82

0xEE

0x83

0xEF

0x83

0xEE

0x84

0xEF

0x84

0xEE

0x85

0xEF

0x85

0xEE

0x86

0xEF

0x86

0xEE

0x87

0xEF

0x87

Wait at least six LMFC cycles.

1

Following this procedure optimizes write and read clock delays of internal FIFO to avoid possible overflow, overtemperature, and supply variations.