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AD9250

Data Sheet

Rev. E | Page 28 of 45

Table 12. JESD204B Configuration Table Used in ILAS and

CHKSUM Calculation

No.

Bit 7

(MSB)

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

(LSB)

DID[7:0]

BID[3:0]

LID[4:0]

SCR

L[4:0]

F[7:0]

K[4:0]

M[7:0]

CS[1:0]

N[4:0]

SUBCLASS[2:0]

N’[4:0]

JESDV[2:0]

S[4:0]

CF[4:0]

Additional Digital Output Configuration Options

Other data format controls include the following:



Invert polarity of serial output data: Register 0x60, Bit 1.



ADC data format (offset binary or twos complement):



Options for interpreting single on SYSREF± and SYNCINB±:



Option to remap converter and lane assignments, Register 0x82

and Register 0x83. See Figure 54 for simplified block diagram.

Re-Enable Lanes After Configuration

After modifying the JESD204B link parameters, enable the link so

that the synchronization process can begin. This is accomplished

by writing Logic 0 to Register 0x5F, Bit 0.

Internal FIFO Timing Optimization

Each lane of the of the AD9250 JESD204B digital path includes

an internal FIFO situated between the framer and serializer,

which operate from two different clock domains, the ADC

sample clock and JESD204B PLL domains. To optimize the

write and read pointers against possible FIFO overflow (or

underflow) under extreme temperature changes and inconsistent

power-up conditions, additional steps are required to increase the

timing margin. The procedures described in Step 15 of Table 19

adjust the write clock phase (via Register 0xEE and Register

0xEF) with respect to the read clock to optimize the timing

margin.

CONVERTER A

CONVERTER B

INPUT

CONVERTER A

INPUT

SYSREF

SYNCINB

CONVERTER B

SAMPLE

CONVERTER A

SAMPLE

AD9250 DUAL ADC

LANE 0

LANE 1

SERDOUT0

SERDOUT1

LANE 1

LANE 0

PRIMARY CONVERTER

INPUT [0]

PRIMARY LANE

OUTPUT [0]

PRIMARY CONVERTER

INPUT [0]

PRIMARY LANE

OUTPUT [0]

JESD204B LANE CONTROL

(M = 1, 2; L = 1, 2)

LANE MUX

(SPI REGISTER

MAPPING: 0x82,0x83)

SECONDARY CONVERTER

INPUT [1]

SECONDARY LANE

OUTPUT [1]

SECONDARY CONVERTER

INPUT [1]

SECONDARY LANE

OUTPUT [1]

JESD204B LANE CONTROL

(M = 1, 2; L = 1, 2)

Figure 54. AD9250 Transmit Link Simplified Block Diagram

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