AD9250 datasheet(26/45 Pages) AD

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AD9250

Data Sheet

Rev. E | Page 26 of 45

JESD204B SYNCHRONIZATION DETAILS

The AD9250 supports JESD204B Subclass 0 and Subclass 1 and

establishes synchronization of the link through one or two

control signals, SYNC and Subclass 1 also use SYSREF, and a

common device clock. SYSREF and SYNC are common to all

converter devices for alignment purposes at the system level.

The synchronization process is accomplished over three phases:

code group synchronization (CGS), initial lane alignment

sequence (ILAS), and data transmission. If scrambling is

enabled, scrambling begins with the first data byte following

the last alignment character of the ILAS. CGS and ILAS

phases are not scrambled.

CGS Phase

In the CGS phase, the JESD204B transmit block transmits

/K28.5/ characters. The receiver (external logic device) must

locate K28.5 characters in its input data stream using clock

and data recovery (CDR) techniques.

When in Subclass 1 mode, the receiver locks onto the K28.5

characters. Once detected, the receiver initiates a SYSREF edge

so that the AD9250 transmit data establishes a local multiframe

clock (LMFC) internally.

The SYSREF edge also resets any sampling edges within the

ADC to align sampling instances to the LMFC. This is important

to maintain synchronization across multiple devices.

If Subclass 0: at the next receiver’s internal clock; if Subclass 1: at

the next receiver’s LMFC boundary, the receiver or logic device

de-asserts the SYNC~ signal (SYNCINB± goes high), and the

transmitter block begins the ILAS phase.

ILAS Phase

In the ILAS phase, the transmitter sends out a known pattern,

and the receiver aligns all lanes of the link and verifies the

parameters of the link.

The ILAS phase begins after SYNC~ has been de-asserted

(goes high). If Subclass 0: the transmitter begins ILAS at the

next transmitter’s internal clock; if Subclass 1: at the next

transmitter’s internal LMFC boundary, the transmit block

begins to transmit four multiframes. Dummy samples are

inserted between the required characters so that full

multiframes are transmitted. The four multiframes include

the following:

•

Multiframe 1: Begins with an /R/ character [K28.0] and

ends with an /A/ character [K28.3].

•

Multiframe 2: Begins with an /R/ character followed by a /Q/

[K28.4] character, followed by link configuration parameters

over 14 configuration octets (see Table 10), and ends with

an /A/ character. Many of the parameters values are of the

notation of the value − 1.

•

Multiframe 3: Is the same as Multiframe 1.

•

Multiframe 4: Is the same as Multiframe 1.

Data Transmission Phase

In the data transmission phase, frame alignment is monitored

with control characters. Character replacement is used at the

end of frames. Character replacement in the transmitter occurs

in the following instances:

•

If scrambling is disabled and the last octet of the frame or

multiframe equals the octet value of the previous frame.

•

If scrambling is enabled and the last octet of the multiframe is

equal to 0x7C, or the last octet of a frame is equal to 0xFC.

Table 10. Fourteen Configuration Octets of the ILAS Phase

No.

Bit 7

(MSB)

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

(LSB)

DID[7:0]

BID[3:0]

LID[4:0]

SCR

L[4:0]

F[7:0]

K[4:0]

M[7:0]

CS[1:0]

N[4:0]

SUBCLASS[2:0]

N’[4:0]

JESDV[2:0]

S[4:0]

CF[4:0]

Reserved, Don’t Care

FCHK[7:0]

LINK SETUP PARAMETERS

The following demonstrates how to configure the AD9250

JESD204B interface paremeters. These details are a subset of the

SPI initialization sequence shown in Figure 63 and Table 19.

The steps to configure the output include the following:

1. Disable lanes before changing the configuration.

2. Select the quick configuration option.

3. Configure the detailed options.

4. Check FCHK, checksum of JESD204B interface parameters.

5. Set the additional digital output configuration options.

6. Re-enable lane(s).

Disable Lanes Before Changing Configuration

Before modifying the JESD204B link parameters, disable the link

and hold it in reset. This is accomplished by writing Logic 1 to

Select Quick Configuration Option

Write to Register 0x5E, the 204B quick configuration register to

select the configuration options. See Table 13 for configuration

options and resulting JESD204B parameter values.

•

0x11 = one converter, one lane

•

0x12 = one converter, two lanes

•

0x21 = two converters, one lane

•

0x22 = two converters, two lanes

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