AD9250 datasheet(24/45 Pages) AD

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AD9250

Data Sheet

Rev. E | Page 24 of 45

Treat the clock input as an analog signal in cases where aperture

jitter may affect the dynamic range of the AD9250. Separate the

power supplies for the clock drivers from the ADC output driver

supplies to avoid modulating the clock signal with digital noise.

Low jitter, crystal controlled oscillators make the best clock

sources. If the clock is generated from another type of source (by

gating, dividing, or another method), retime it by the original

clock at the last step.

Refer to the AN-501 Application Note, Aperture Uncertainty and

ADC System Performance and the AN-756 Application Note,

Sampled Systems and the Effects of Clock Phase Noise and Jitter for

more information about jitter performance as it relates to ADCs.

POWER DISSIPATION AND STANDBY MODE

As shown in Figure 53, the power dissipated by the AD9250 is

proportional to its sample rate. The data in Figure 53 was taken

using the same operating conditions as those used for the Typical

Performance Characteristics section.

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

140

190

240

POWER (AVDD)

POWER (DVDD)

TOTAL POWER

ENCODE FREQUENCY (MSPS)

Figure 53. AD9250-250 Power vs. Encode Rate

By asserting PDWN (either through the SPI port or by asserting

the PDWN pin high), the AD9250 is placed in power-down mode.

In this state, the ADC typically dissipates about 9 mW. Asserting the

PDWN pin low returns the AD9250 to its normal operating mode.

Low power dissipation in power-down mode is achieved by

shutting down the reference, reference buffer, biasing networks,

and clock. Internal capacitors are discharged when entering power-

down mode and then must be recharged when returning to normal

operation. As a result, wake-up time is related to the time spent

in power-down mode, and shorter power-down cycles result in

proportionally shorter wake-up times.

When using the SPI port interface, the user can place the ADC

in power-down mode or standby mode. Standby mode allows

the user to keep the internal reference circuitry powered when

faster wake-up times are required. See the Memory Map Register

Description section and the AN-877 Application Note,

Interfacing to High Speed ADCs via SPI, for additional details.

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