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AD9250 Datasheet(PDF) 22 Page - Analog Devices |
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AD9250 Datasheet(HTML) 22 Page - Analog Devices |
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22 / 45 page  AD9250 Data Sheet Rev. E | Page 22 of 45 Nyquist Clock Input Options The AD9250 Nyquist clock input supports a differential clock between 40 MHz to 625 MHz. The clock input structure supports differential input voltages from 0.3 V to 3.6 V and is therefore compatible with various logic family inputs, such as CMOS, LVDS, and LVPECL. A sine wave input is also accepted, but higher slew rates typically provide optimal performance. Clock source jitter is a critical parameter that can affect performance, as described in the Jitter Considerations section. If the inputs are floated, pull the CLK− pin low to prevent spurious clocking. The Nyquist clock input pins, CLK+ and CLK−, are internally biased to 0.9 V and have a typical input impedance of 4 pF in parallel with 10 kΩ (see Figure 43). The input clock is typically ac-coupled to CLK+ and CLK−. Some typical clock drive circuits are presented in Figure 44 through Figure 47 for reference. AVDD CLK+ 4pF 4pF CLK– 0.9V Figure 43. Equivalent Nyquist Clock Input Circuit For applications where a single-ended low jitter clock between 40 MHz to 200 MHz is available, an RF transformer is recom- mended. An example using an RF transformer in the clock network is shown in Figure 44. At frequencies above 200 MHz, an RF balun is recommended, as seen in Figure 45. The back-to-back Schottky diodes across the transformer secondary limit clock excursions into the AD9250 to approximately 0.8 V p-p differential. This limit helps prevent the large voltage swings of the clock from feeding through to other portions of the AD9250, yet preserves the fast rise and fall times of the clock, which are critical to low jitter performance. 390pF 390pF 390pF SCHOTTKY DIODES: HSMS2822 CLOCK INPUT 50 Ω 100 Ω CLK– CLK+ ADC Mini-Circuits® ADT1-1WT, 1:1Z XFMR Figure 44. Transformer-Coupled Differential Clock (Up to 200 MHz) 390pF 390pF 390pF CLOCK INPUT 1nF 25 Ω 25 Ω CLK– CLK+ SCHOTTKY DIODES: HSMS2822 ADC Figure 45. Balun-Coupled Differential Clock (Up to 625 MHz) In some cases, it is desirable to buffer or generate multiple clocks from a single source. In those cases, Analog Devices, Inc., offers clock drivers with excellent jitter performance. Figure 46 shows a typical PECL driver circuit that uses PECL drivers such as the AD9510, AD9511, AD9512, AD9513, AD9514, AD9515, AD9516-0 through AD9516-5 device family, AD9517-0 through AD9517-4 device family, AD9518-0 through AD9518-4 device family, AD9520-0 through AD9520-5 device family, AD9522-0 through AD9522-5 device family, AD9523, AD9524, and ADCLK905/ADCLK907/ADCLK925 100 Ω 0.1µF 0.1µF 0.1µF 0.1µF 240 Ω 240 Ω PECL DRIVER 50k Ω 50k Ω CLK– CLK+ CLOCK INPUT CLOCK INPUT AD95xx ADC Figure 46. Differential PECL Sample Clock (Up to 625 MHz) Analog Devices also offers LVDS clock drivers with excellent jitter performance. A typical circuit is shown in Figure 47 and uses LVDS drivers such as the AD9510, AD9511, AD9512, AD9513, AD9514, AD9515, AD9516-0 through AD9516-5 device family, AD9517-0 through AD9517-4 device family, AD9518-0 through AD9518-4 device family, AD9520-0 through AD9520-5 device family, AD9522-0 through AD9522-5 device family, AD9523, and AD9524. 100 Ω 0.1µF 0.1µF 0.1µF 0.1µF 50k Ω 50k Ω CLK– CLK+ CLOCK INPUT CLOCK INPUT AD95xx LVDS DRIVER ADC Figure 47. Differential LVDS Sample Clock (Up to 625 MHz) RF Clock Input Options The AD9250 RF clock input supports a single-ended clock between 625 GHz to 1.5 GHz. The equivalent RF clock input circuit is shown in Figure 48. The input is self biased to 0.9 V and is typically ac-coupled. The input has a typical input impedance of 10 kΩ in parallel with 1 pF at the RFCLK pin. BIAS CONTROL 10k Ω RFCLK INTERNAL CLOCK DRIVER 1pF Figure 48. Equivalent RF Clock Input Circuit It is recommended to drive the RF clock input of the AD9250 with a PECL or sine wave signal with a minimum signal amplitude of 600 mV peak to peak. Regardless of the type of signal being used, clock source jitter is of the most concern, as described in the Jitter Considerations section. Figure 49 shows the preferred method of clocking when using the RF clock input on the AD9250. It is recommended to use a 50 Ω transmission line to route the clock signal to the RF clock input of the AD9250 due to the high frequency nature of the signal and terminate the transmission line close to the RF clock input. RFCLK ADC 50 Ω Tx LINE RF CLOCK INPUT 0.1µF 50 Ω Figure 49. Typical RF Clock Input Circuit |
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