AD9250 datasheet(38/45 Pages) AD

38 / 45 page

AD9250

Data Sheet

Rev. E | Page 38 of 45

Reg

Addr

(Hex)

Name

Bit 7

(MSB)

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0 (LSB)

Default

Notes

0x10

Customer

offset

(local)

Offset adjust in LSBs from +31 to −32 (twos complement format);

01 1111 = adjust output by +31;

01 1110 = adjust output by +30;

…

00 0001 = adjust output by +1;

00 0000 = adjust output by 0 (default);

…

10 0001 = adjust output by −31;

10 0000 = adjust output by −32

0x00

Local

0x14

Output

mode

(local)

JTX CS bits assignment (in

conjunction with Register 0x72)

000 = (overrange||underrange, valid)

001 = (overrange||underrange)

010 = (overrange||underrange, blank)

011 = (blank, valid)

100 = (blank, blank)

All others = (overrange||underrange,

valid)

Disable

output

from ADC

Invert ADC

data;

0 = normal

(default);

1 =

inverted

Digital datapath output

data format select (DFS)

(local);

00 = offset binary;

01 = twos complement

0x01

Local

0x15

CML output

adjust

JESD204B CML differential output drive

level adjustment;

000 = 81% of nominal (that is, 478 mV);

001 = 89% of nominal (that is, 526 mV);

010 = 98% of nominal (that is, 574 mV);

011 = nominal (default) (that is, 588 mV);

110 = 126% of nominal (that is, 738 mV)

0x03

0x18

ADC VREF

Main reference full-scale VREF adjustment;

0 1111 = internal 2.087 V p-p;

…

0 0001 = internal 1.772 V p-p;

0 0000 = internal 1.75 V p-p (default);

1 1111 = internal 1.727 V p-p;

…

1 0000 = internal 1.383 V p-p

0x00

Local

0x19

User Test

Pattern 1 L

User Test Pattern 1 LSB; use in conjunction with Register 0x0D and Register 0x61

0x00

0x1A

User Test

Pattern 1 M

User Test Pattern 1 MSB

0x00

0x1B

User Test

Pattern 2 L

User Test Pattern 2 LSB

0x00

0x1C

User Test

Pattern 2 M

User Test Pattern 2 MSB

0x00

0x1D

User Test

Pattern 3 L

User Test Pattern 3 LSB

0x00

0x1E

User Test

Pattern 3 M

User Test Pattern 3 MSB

0x00

0x1F

User Test

Pattern 4 L

User Test Pattern 4 LSB

0x00

0x20

User Test

Pattern 4 M

User Test Pattern 4 MSB

0x00

0x21

PLL low

encode

00 = for lane speeds >

2 Gbps;

01 = for lane speeds <

2 Gbps

0x00

AD9250 Datasheet(PDF) 38 Page - Analog Devices

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