AD9250 datasheet(41/45 Pages) AD

41 / 45 page

Data Sheet

AD9250

Rev. E | Page 41 of 45

Reg

Addr

(Hex)

Name

Bit 7

(MSB)

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0 (LSB)

Default

Notes

0x73

204B

parameters

subclass/Np

JESD204B subclass;

0x0 = Subclass 0;

0x1 = Subclass 1

(default)

JESD204B N’ value; 0xF = N’ = 16

(Note that this value is in x – 1 format)

0x2F

0x74

204B

parameters S

Reserved;

set to 1

JESD204B samples per converter frame cycle (S); read only

(Note that this value is in x − 1 format)

0x20

0x75

204B

parameters

HD and CF

JESD204B

HD value;

read only

JESD204B control words per frame clock cycle per link (CF);

read only

0x00

Read

Only

0x76

204B RESV1

Reserved Field Number 1

0x00

0x77

204B RESV2

Reserved Field Number 2

0x00

0x78

204B

CHKSUM0

JESD204B serial checksumvalue for Lane 0

0x42

0x79

204B

CHKSUM1

JESD204B serial checksumvalue for Lane 1

0x43

0x82

204B Lane

Assign 1

00 = assign Logical Lane 0

to Physical Lane A

(default);

01 = assign Logical Lane 0

to Physical Lane B

Reserved;

set to 1

Reserved;

set to 0

0x02

0x83

204B Lane

Assign 2

Reserved;

set to 1

Reserved;

set to 1

00 = assign Logical Lane

1 to Physical Lane A;

01 = assign Logical Lane 1

to Physical Lane B

(default)

0x31

0x8B

204B LMFC

offset

Local multiframe clock (LMFC) phase offset value; reset value for

LMFC phase counter when SYSREF is asserted; used for

deterministic delay applications

0x00

0xA8

204B pre-

emphasis

JESD204B pre-emphasis enable option (consult factory for more detail);

set value to 0x04 for pre-emphasis off;

set value to 0x14 for pre-emphasis on

0x04

Typically

not

required

0xEE

Internal

digital clock

delay

Enable

internal

clock delay

Set to 0

Use incrementing values from 0 to 7 to increase

internal digital clock delay. For internal data latching

purposes, this does not affect external timing.

0x00

See

JESD

Section

for use

0xEF

Internal

digital clock

delay

Enable

internal

clock delay

Set to 0

Use incrementing values from 0 to 7 to increase

internal digital clock delay. For internal data latching

purposes, this does not affect external timing.

0x00

See

JESD

Section

for use

0xF3

Internal

digital clock

alignment

Force

manual

re-align

on Lane 1,

self

clearing

Lane 1

Alignment

complete

Force

manual

realign on

Lane 0,

self

clearing

Lane 0

alignment

complete

0x14

See

JESD

Section

for use

0xFF

Device

update

(global)

Transfer

settings

MEMORY MAP REGISTER DESCRIPTION

For more information on functions controlled in Register 0x00

to Register 0x25, see the AN-877 Application Note, Interfacing

to High Speed ADCs via SPI.

AD9250 Datasheet(PDF) 41 Page - Analog Devices

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