AD9250 datasheet(43/45 Pages) AD

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Data Sheet

AD9250

Rev. E | Page 43 of 45

SET THE QUICK JESD204

CONFIGURATION MODE

(REFER TO TABLE 13)

RESET INTERNAL CLOCKS

TO MINIMUM SETTING

FIFO WRITE/READ

CLOCK ADJUSTMENT

WAIT >6LMFC CLOCKS

OPTIONAL

MODIFY ANY OTHER

JESD204B PARAMETERS

FROM DEFAULT SETTING

DISABLE THE JESD204B

TxPHY DURING SET-UP

(AS WELL AS JESD204B Rx)

APPLY POWER AND CLOCK

ALLOW TIME TO SETTLE

ISSUE SOFTWARE RESET

THEN WAIT 500µs MIN

ISSUE SOFTWARE

POWER-DOWN

SET DIVIDER VALUE

OPTIONAL

CONFIGURE ANY

NON-JESD204

REGISTERS FROM

DEFAULT SETTING

USE CLOCK

DIVIDER?

YES

ISSUE SOFTWARE

POWER-UP

WAIT 250ms

USE CLOCK

DIVIDER?

YES

JESD204B

SUBCLASS1

SYNC

YES

ENABLE

SYSREF BUFFER

CONFIGURE

SYSREF MODE

READBACKPLL LOCK BIT

ENABLE PHY TO BEGIN CGS PHASE

FORCE FIFO ALIGNMENT

WAIT >6LMFC CLOCKS

APPLY EXTERNAL SYSREF

WAIT >6LMFC CLOCKS

DISABLE SYSREF BUFFER

(ONE-SHOT MODE ONLY)

JESD204B

SUBCLASS1

SYNC

YES

Figure 63. Flowchart Showing Sequence of Steps Required to Initialize the AD9250

Table 19. SPI Initialization Sequence

Step

Address

Write

Value

Comments

Apply power to the AD9250 and allow the voltages and clocks to stabilize.

0x00

0x3C

Software reset.

Wait 500 μs minimum.

0x5F

0x15

Disable the JESD204B PHY.

Optional: modify any other non-JESD204B register from default setting depending on application

requirements. Note, any local register must be followed by a transfer command (0xFF= 0x01)

0x0B

0x01

Optional: set the clock divider ratio if using a clock divider. Note that the 0x01 value shown corresponds to a

divide-by-2 clock ratio.

0xFF

0x01

Transfer command for local Register

0x5E

0xML

Set the JESD204B quick configuration register based on the desired M and L values.

0xEE

0x80

Enable the internal clock delay block for minimum delay.

0x21

0x00

Conditional: configure the PLL low encode register. Only set to 0x01 if the lane rate is < 2 GBPS. The default

setting is 0x00.

Optional: modify the JESD204B centric registers from the default setting as follows:

0x14

0x01

Configure the data output with 0x01 being the default (twos complement).

0x15

0x03

Set the JESD204B CML differential drive level with 0x03 being default (588 mV).

0x66

0x00

Set the Lane 0 and Lane 1 LID value (defaults shown).

0x67

0x01

Set the Lane 0 and Lane 1 LID value (defaults shown).

0x6E

0x81

Enable the JESD204B scrambling in Bit 7 while keeping desired JESD204B lane value, L, in Bit 0. Default shown.

0x70

0x1F

Modify the JESD204B K and CS values. Default shown.

0x82

0x0D

Modify the JESD204B K and CS values. Default shown.

Modify other JESD204B centric configurations in Register 0x82 to Register 0x8B and Register 0xA8.

0xFF

0x01

Transfer command for local Register

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