AD9250 datasheet(31/45 Pages) AD

31 / 45 page

Data Sheet

AD9250

Rev. E | Page 31 of 45

The AD9250 digital outputs can interface with custom ASICs and

FPGA receivers, providing superior switching performance in

noisy environments. Single point-to-point network topologies are

recommended with a single differential 100 Ω termination resistor

placed as close to the receiver logic as possible. The common mode

of the digital output automatically biases itself to half the supply

of the receiver (that is, the common-mode voltage is 0.9 V for a

receiver supply of 1.8 V) if dc-coupled connecting is used (see

Figure 58). For receiver logic that is not within the bounds of

the DRVDD supply, use an ac-coupled connection. Simply place

a 0.1 µF capacitor on each output pin and derive a 100 Ω

differential termination close to the receiver side.

100Ω

DIFFERENTIAL

TRACE PAIR

DRVDD

VCM = DRVDD/2

RECEIVER

SERDOUTx+

SERDOUTx–

OUTPUT SWING = VOD

(SEE TABLE 3)

Figure 58. DC-Coupled Digital Output Termination Example

If there is no far-end receiver termination, or if there is poor

differential trace routing, timing errors may result. To avoid

such timing errors, it is recommended that the trace length be

less than six inches, and that the differential output traces be

close together and at equal lengths.

Figure 59 shows an example of the digital output (default) data eye

and time interval error (TIE) jitter histogram and bathtub curve

for the AD9250 lane running at 5 Gbps.

Additional SPI options allow the user to further increase the

output driver voltage swing of all four outputs to drive longer

trace lengths (see Register 0x15 in Table 18). The power

dissipation of the DRVDD supply increases when this option is

used. See the Memory Map section for more details.

The format of the output data is twos complement by default.

To change the output data format to offset binary, see the

Memory Map section (Register 0x14 in Table 18).

–0.5

0.5

UIs

PERIOD1: HISTOGRAM

6000

7000

–10

TIME (ps)

5000

4000

1000

2000

3000

1–16

1–14

1–12

1–10

1–8

1–6

1–4

1–2

–

–100

–200

100

200

TIME (ps)

400

300

200

100

–100

–300

–400

–200

HEIGHT1: EYE DIAGRAM

–

TJ@BER1: BATHTUB

EYE: TRANSITION BITS OFFSET: –0.0072

UIs: 8000; 999992 TOTAL: 8000.999992

0.78 UI

Figure 59. AD9250 Digital Outputs Data Eye, Histogram and Bathtub, External 100 Ω Terminations at 5 Gbps

–0.5

0.5

UIs

PERIOD1: HISTOGRAM

4000

4500

–10

TIME (ps)

3500

3000

1000

2000

2500

1500

500

1–16

1–14

1–12

1–10

1–8

1–6

1–4

1–2

–

–250

–150

–50

150

250

TIME (ps)

400

300

200

100

–100

–300

–400

–200

HEIGHT1: EYE DIAGRAM

–

TJ@BER1: BATHTUB

0.84 UI

EYE: TRANSITION BITS OFFSET: 0

UIs: 8000; 679999 TOTAL: 8000; 679999

Figure 60. AD9250 Digital Outputs Data Eye, Histogram and Bathtub, External 100 Ω Terminations at 3.4 Gbps

AD9250 Datasheet(PDF) 31 Page - Analog Devices

AD9250 Datasheet(HTML) 31 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45

Datasheet Download

Link URL