SL1919 datasheet(2/70 Pages) ZILOG

2 / 70 page

Z80180/Z8S180/Z8L180

Enhanced Z180 Microprocessor

Zilog

1-2

P R E L I M I N A R Y

DS971800401

Notes: All Signals with a preceding front slash, “/” are ac-

tive Low, for example, B//W (WORD is active Low); /B/W

(BYTE is active Low, only). Alternatively, an overslash

may be used to signify active Low, for example WR

Power connections follow conventional descriptions be-

low:

Connection

Circuit

Device

Power

VCC

VDD

Ground

GND

VSS

Figure 1. Z80180/Z8S180/Z8L180 Functional Block Diagram

16-bit

Programmable

Reload Timers

(2)

Clocked

Serial I/O

Port

MMU

Bus State Control

CPU

Interrupt

TXS

RXS/CTS1

CKS

A18/TOUT

DMACS

(2)

Asynchronous

SCI

(Channel 0)

Asynchronous

SCI

(Channel 1)

/DREQ1

TEND1

TXA0

CKA0, /DREQ0

RXA0

/RTS0

/CTS0

/DCD0

TXA1

CKA1, /TEND0

RXA1

Timing

Generator

Data

Buffer

Address

Buffer

VCC

VSS

A19-A0

D7-D0

SL1919 Datasheet(PDF) 2 Page - Zilog, Inc.

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