MFC2000 datasheet(213/426 Pages) ETC

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Multifunctional Peripheral Controller 2000

MFC2000

100723A

Conexant

9-1

9. BI-LEVEL RESOLUTION CONVERSION

9.1

Functional Description

The bi-level resolution conversion logic in the MFC2000 performs expansion (converting from lower to higher

resolution) and reduction (converting from higher to lower resolution) of horizontal image data. Vertical line ORing

can also be performed for image reduction in the vertical direction. There are two data sources that can be

selected for this bi-level resolution conversion block. One is T4/T6 Decompressor and another is the external

memory. The data from the T4/T6 Decompressor is serially input to this bi-level resolution conversion logic. The

data from the external memory is input to this bi-level resolution conversion logic through the DMA operation. The

DMA operation for the data from the external memory uses the DMA channel 9. If the T4/T6 Decompressor is

selected as the data source, the DMA channel 9 request is blocked. The data from this resolution conversion logic

is output to the external memory also through the DMA operation. The DMA operation for the output data uses the

DMA channel 8 (See Figure 9-1).

The MFC2K adds the following features to the BRC Block:

A first and last black data detector to indicate the first and last halfword out of the BRC that contains printable

data.

The ability the change the ORing algorithm for hoizontal reduction.

Because the bi-level resolution conversion is a slave logic, the DMA channel 9 for inputting data from memory has

the block size control function. Once the block size limit is reached during the DMA operation. The DMA

Controller gives a signal to the bi-level resolution conversion logic that indicates the end of process. Then, the bi-

level resolution conversion logic will deactivate the DMA request, disable the FIFO, and start the flush operation.

After the flush operation the bi-level resolution conversion interrupt will be generated to the Interrupt Controller.

Before CPU gets out of the interrupt routine, CPU needs to write the new block size into the DMA9BlockSize

then, immediately write a 0 to bit 1 of the BiResConvCtrl register to tell hardware to convert a new line (Reset the

Resolution Conversion Logic).

If the data from the T4/T6 Decompressor is serially input to this bi-level resolution conversion logic, this bi-level

resolution conversion logic is treated as a part of T.4/T6 logic. The T.4 line length (instead of block size of DMA

channel 9) and T.4 interrupt (instead of the bi-level resolution conversion interrupt) are used. Furthermore,, this bi-

level resolution conversion logic is enabled by setting bit 5 in the ‘T4Config’ register in the T4/T6

Compression/Decompression Logic.

The flush operation depends on the FIFO direction. If the FIFO is being read by the local side and written by the

system side, a flush will simply reset all of the internal FIFO pointers, thereby removing the data. If the FIFO is

being written by the local side and read by the system side, a flush will cause a DMA request to be generated. In

addition, if there is a single byte in the holding register, it will be treated as a halfword (the contents of the msbyte

of the halfword are indeterminate). Because of this, it is important for firmware to first check for the presence of a

single byte in the holding register (via the Byte Present bit in the FIFO Control register).

Each FIFO is composed of 4 halfwords, a holding register, and a control register. Firmware can randomly access

all the FIFO registers under the following restrictions:

•

When the FIFO is enabled - reads may return invalid data, writes are blocked

•

When the FIFO is disabled - read/write operations are properly performed

•

Random access of the FIFO registers is useful in saving and restoring the state of the FIFO. This should only

be done when the FIFO is disabled.

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